CoCalc -- exynos-pinctrl.h

GitHub Repository: torvalds/linux
Path: blob/master/arch/arm64/boot/dts/exynos/exynos-pinctrl.h
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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 * Samsung Exynos DTS pinctrl constants
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 *
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 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
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 *		http://www.samsung.com
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 * Copyright (c) 2022 Linaro Ltd
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 * Author: Krzysztof Kozlowski <[email protected]>
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 */
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#ifndef __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__
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#define __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__
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#define EXYNOS_PIN_PULL_NONE		0
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#define EXYNOS_PIN_PULL_DOWN		1
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#define EXYNOS_PIN_PULL_UP		3
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/* Pin function in power down mode */
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#define EXYNOS_PIN_PDN_OUT0		0
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#define EXYNOS_PIN_PDN_OUT1		1
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#define EXYNOS_PIN_PDN_INPUT		2
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#define EXYNOS_PIN_PDN_PREV		3
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/*
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 * Drive strengths for Exynos5410, Exynos542x, Exynos5800, Exynos7885, Exynos850
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 * (except GPIO_HSI block), ExynosAutov9 (FSI0, PERIC1)
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 */
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#define EXYNOS5420_PIN_DRV_LV1		0
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#define EXYNOS5420_PIN_DRV_LV2		1
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#define EXYNOS5420_PIN_DRV_LV3		2
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#define EXYNOS5420_PIN_DRV_LV4		3
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/* Drive strengths for Exynos5433 */
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#define EXYNOS5433_PIN_DRV_FAST_SR1	0
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#define EXYNOS5433_PIN_DRV_FAST_SR2	1
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#define EXYNOS5433_PIN_DRV_FAST_SR3	2
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#define EXYNOS5433_PIN_DRV_FAST_SR4	3
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#define EXYNOS5433_PIN_DRV_FAST_SR5	4
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#define EXYNOS5433_PIN_DRV_FAST_SR6	5
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#define EXYNOS5433_PIN_DRV_SLOW_SR1	8
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#define EXYNOS5433_PIN_DRV_SLOW_SR2	9
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#define EXYNOS5433_PIN_DRV_SLOW_SR3	0xa
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#define EXYNOS5433_PIN_DRV_SLOW_SR4	0xb
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#define EXYNOS5433_PIN_DRV_SLOW_SR5	0xc
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#define EXYNOS5433_PIN_DRV_SLOW_SR6	0xf
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/* Drive strengths for Exynos7 (except FSYS1) */
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#define EXYNOS7_PIN_DRV_LV1		0
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#define EXYNOS7_PIN_DRV_LV2		2
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#define EXYNOS7_PIN_DRV_LV3		1
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#define EXYNOS7_PIN_DRV_LV4		3
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/* Drive strengths for Exynos7 FSYS1 block */
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#define EXYNOS7_FSYS1_PIN_DRV_LV1	0
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#define EXYNOS7_FSYS1_PIN_DRV_LV2	4
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#define EXYNOS7_FSYS1_PIN_DRV_LV3	2
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#define EXYNOS7_FSYS1_PIN_DRV_LV4	6
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#define EXYNOS7_FSYS1_PIN_DRV_LV5	1
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#define EXYNOS7_FSYS1_PIN_DRV_LV6	5
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/* Drive strengths for Exynos850 GPIO_HSI block */
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#define EXYNOS850_HSI_PIN_DRV_LV1	0	/* 1x   */
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#define EXYNOS850_HSI_PIN_DRV_LV1_5	1	/* 1.5x */
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#define EXYNOS850_HSI_PIN_DRV_LV2	2	/* 2x   */
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#define EXYNOS850_HSI_PIN_DRV_LV2_5	3	/* 2.5x */
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#define EXYNOS850_HSI_PIN_DRV_LV3	4	/* 3x   */
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#define EXYNOS850_HSI_PIN_DRV_LV4	5	/* 4x   */
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#define EXYNOS_PIN_FUNC_INPUT		0
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#define EXYNOS_PIN_FUNC_OUTPUT		1
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#define EXYNOS_PIN_FUNC_2		2
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#define EXYNOS_PIN_FUNC_3		3
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#define EXYNOS_PIN_FUNC_4		4
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#define EXYNOS_PIN_FUNC_5		5
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#define EXYNOS_PIN_FUNC_6		6
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#define EXYNOS_PIN_FUNC_EINT		0xf
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#define EXYNOS_PIN_FUNC_F		EXYNOS_PIN_FUNC_EINT
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#endif /* __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__ */
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