fsl-ls1028a-tqmls1028a-mbls1028a.dtsi

// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
 * Copyright 2019-2025 TQ-Systems GmbH <[email protected]>,
 * D-82229 Seefeld, Germany.
 * Author: Michael Krummsdorf
 * Author: Matthias Schiffer
 * Author: Alexander Stein
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "fsl-ls1028a-tqmls1028a.dtsi"

/ {
	aliases {
		crypto = &crypto;
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		mmc0 = &esdhc; /* SD-Card */
		mmc1 = &esdhc1; /* eMMC */
		serial0 = &duart0;
		serial1 = &duart1;
	};

	chosen {
		stdout-path = &duart0;
	};

	reg_1p8v: regulator-1p8v {
		compatible = "regulator-fixed";
		regulator-name = "V_1V8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "V_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/* global autoconfigured region for contiguous allocations */
		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			/* 256 MiB */
			size = <0 0x10000000>;
			linux,cma-default;
		};
	};
};

&can0 {
	status = "okay";
};

&can1 {
	status = "okay";
};

&dspi2 {
	bus-num = <2>;
	status = "okay";
};

&duart0 {
	status = "okay";
};

&duart1 {
	status = "okay";
};

&esdhc {
	cd-gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
	disable-wp;
	no-mmc;
	no-sdio;
	no-1-8-v;
	bus-width = <4>;
	status = "okay";
};

/* When switched to baseboard-internal i2c bus,
 * IIC5 has access to the following devices.
 */
&i2c4 {
	/* TUSB8041 only supports 100 KHz, but it is not connected */
	clock-frequency = <400000>;
	status = "okay";

	/* SI5338 - set up in U-Boot */
	/* clockgen@70 */
};

&i2c5 {
	clock-frequency = <400000>;
	status = "okay";

	gpio_exp_1v8: gpio@70 {
		compatible = "nxp,pca9538";
		reg = <0x70>;
		#gpio-cells = <2>;
		gpio-controller;
		#interrupt-cells = <2>;
		interrupt-controller;
		interrupt-parent = <&gpio1>;
		interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
		vcc-supply = <&reg_1p8v>;

		ec1-intn-hog {
			gpio-hog;
			gpios = <0 0>;
			input;
			line-name = "EC1_INT#";
		};

		sgmii-intn-hog {
			gpio-hog;
			gpios = <2 0>;
			input;
			line-name = "SGMII_INT#";
		};

		qsgmii-intn-hog {
			gpio-hog;
			gpios = <4 0>;
			input;
			line-name = "QSGMII_INT#";
		};

		qsgmii-rstn-hog {
			gpio-hog;
			gpios = <5 0>;
			output-high;
			line-name = "QSGMII_RESET#";
		};
	};
};

&enetc_mdio_pf3 {
	mdio0_rgmii_phy00: ethernet-phy@0 {
		compatible = "ethernet-phy-ieee802.3-c22";
		reg = <0x00>;
		reset-gpios = <&gpio_exp_1v8 1 GPIO_ACTIVE_LOW>;
		reset-assert-us = <1>;
		reset-deassert-us = <200>;
		interrupt-parent = <&gpio_exp_1v8>;
		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
		ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
	};

	mdio0_sgmii_phy03: ethernet-phy@3 {
		compatible = "ethernet-phy-ieee802.3-c22";
		reg = <0x03>;
		reset-gpios = <&gpio_exp_1v8 3 GPIO_ACTIVE_LOW>;
		/*
		 * Long reset to work around PHY incorrect strap pin sampling
		 * due to external capacitors for SGMII
		 */
		reset-assert-us = <2500>;
		reset-deassert-us = <200>;
		interrupt-parent = <&gpio_exp_1v8>;
		interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
		ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
	};

	qsgmii_phy1: ethernet-phy@1c {
		reg = <0x1c>;
	};

	qsgmii_phy2: ethernet-phy@1d {
		reg = <0x1d>;
	};

	qsgmii_phy3: ethernet-phy@1e {
		reg = <0x1e>;
	};

	qsgmii_phy4: ethernet-phy@1f {
		reg = <0x1f>;
	};
};

&enetc_port0 {
	phy-handle = <&mdio0_sgmii_phy03>;
	phy-mode = "sgmii";
	managed = "in-band-status";
	status = "okay";
};

&enetc_port1 {
	phy-handle = <&mdio0_rgmii_phy00>;
	phy-mode = "rgmii-id";
	status = "okay";
};

&enetc_port2 {
	status = "okay";
};

&mscc_felix {
	status = "okay";
};

/* l2switch ports */
&mscc_felix_port0 {
	phy-handle = <&qsgmii_phy1>;
	phy-mode = "qsgmii";
	status = "okay";
};

&mscc_felix_port1 {
	phy-handle = <&qsgmii_phy2>;
	phy-mode = "qsgmii";
	status = "okay";
};

&mscc_felix_port2 {
	phy-handle = <&qsgmii_phy3>;
	phy-mode = "qsgmii";
	status = "okay";
};

&mscc_felix_port3 {
	phy-handle = <&qsgmii_phy4>;
	phy-mode = "qsgmii";
	status = "okay";
};

&mscc_felix_port4 {
	ethernet = <&enetc_port2>;
	status = "okay";
};

&pcie2 {
	status = "okay";
};

&sata {
	status = "okay";
};

&usb0 {
	/* dual role is implemented, but not a full featured OTG */
	hnp-disable;
	srp-disable;
	adp-disable;
	dr_mode = "otg";
	status = "okay";
};

&usb1 {
	dr_mode = "host";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	hub_2_0: hub@1 {
		compatible = "usb451,8142";
		reg = <1>;
		peer-hub = <&hub_3_0>;
		reset-gpios = <&gpio_exp_3v3 1 GPIO_ACTIVE_LOW>;
		vdd-supply = <&reg_3p3v>;
	};

	hub_3_0: hub@2 {
		compatible = "usb451,8140";
		reg = <2>;
		peer-hub = <&hub_2_0>;
		reset-gpios = <&gpio_exp_3v3 1 GPIO_ACTIVE_LOW>;
		vdd-supply = <&reg_3p3v>;
	};
};