kent.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * Realtek Kent SoC family
 *
 * Copyright (c) 2024 Realtek Semiconductor Corp.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &uart0;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI  9 IRQ_TYPE_LEVEL_HIGH>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a78";
			reg = <0x0>;
			enable-method = "psci";
			next-level-cache = <&l2_0>;
			dynamic-power-coefficient = <454>;
			#cooling-cells = <2>;

			l2_0: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-line-size = <64>;
				cache-sets = <256>;
				cache-size = <0x40000>;
				cache-unified;
				next-level-cache = <&l3>;
			};
		};

		cpu1: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a78";
			reg = <0x100>;
			enable-method = "psci";
			next-level-cache = <&l2_1>;
			dynamic-power-coefficient = <454>;
			#cooling-cells = <2>;

			l2_1: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-line-size = <64>;
				cache-sets = <256>;
				cache-size = <0x40000>;
				cache-unified;
				next-level-cache = <&l3>;
			};
		};

		cpu2: cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a78";
			reg = <0x200>;
			enable-method = "psci";
			next-level-cache = <&l2_2>;
			dynamic-power-coefficient = <454>;
			#cooling-cells = <2>;

			l2_2: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-line-size = <64>;
				cache-sets = <256>;
				cache-size = <0x40000>;
				cache-unified;
				next-level-cache = <&l3>;
			};
		};

		cpu3: cpu@300 {
			device_type = "cpu";
			compatible = "arm,cortex-a78";
			reg = <0x300>;
			enable-method = "psci";
			next-level-cache = <&l2_3>;
			dynamic-power-coefficient = <454>;
			#cooling-cells = <2>;

			l2_3: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-line-size = <64>;
				cache-sets = <256>;
				cache-size = <0x40000>;
				cache-unified;
				next-level-cache = <&l3>;
			};
		};

		l3: l3-cache {
			compatible = "cache";
			cache-level = <3>;
			cache-line-size = <64>;
			cache-sets = <512>;
			cache-size = <0x200000>;
			cache-unified;
		};
	};

	psci: psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	soc@0 {
		compatible = "simple-bus";
		ranges = <0x0 0x0 0x0 0x40000>, /* boot code */
			 <0x98000000 0x0 0x98000000 0xef0000>, /* rbus */
			 <0xa0000000 0x0 0xa0000000 0x10000000>, /* PCIE */
			 <0xff000000 0x0 0xff000000 0x200000>; /* GIC */
		#address-cells = <1>;
		#size-cells = <1>;

		rbus: bus@98000000 {
			compatible = "simple-bus";
			ranges = <0x0 0x98000000 0xef0000>,
				 <0xa0000000 0xa0000000 0x10000000>; /* PCIE */
			#address-cells = <1>;
			#size-cells = <1>;

			uart0: serial@7800 {
				compatible = "snps,dw-apb-uart";
				reg = <0x7800 0x100>;
				clock-frequency = <432000000>;
				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <4>;
				reg-shift = <2>;
				status = "disabled";
			};
		};

		gic: interrupt-controller@ff100000 {
			compatible = "arm,gic-v3";
			reg = <0xff100000 0x10000>,
			      <0xff140000 0x80000>;
			interrupt-controller;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#interrupt-cells = <3>;
			#size-cells = <1>;
		};
	};
};