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torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/arch/loongarch/include/asm/cacheflush.h
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/* SPDX-License-Identifier: GPL-2.0 */

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/*

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 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited

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 */

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#ifndef _ASM_CACHEFLUSH_H

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#define _ASM_CACHEFLUSH_H

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#include <linux/mm.h>

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#include <asm/cpu-info.h>

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#include <asm/cacheops.h>

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static inline bool cache_present(struct cache_desc *cdesc)

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{

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	return cdesc->flags & CACHE_PRESENT;

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}

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static inline bool cache_private(struct cache_desc *cdesc)

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{

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	return cdesc->flags & CACHE_PRIVATE;

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}

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static inline bool cache_inclusive(struct cache_desc *cdesc)

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{

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	return cdesc->flags & CACHE_INCLUSIVE;

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}

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static inline unsigned int cpu_last_level_cache_line_size(void)

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{

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	int cache_present = boot_cpu_data.cache_leaves_present;

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	return boot_cpu_data.cache_leaves[cache_present - 1].linesz;

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}

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asmlinkage void __flush_cache_all(void);

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void local_flush_icache_range(unsigned long start, unsigned long end);

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#define flush_icache_range	local_flush_icache_range

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#define flush_icache_user_range	local_flush_icache_range

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#define flush_cache_all()				do { } while (0)

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#define flush_cache_mm(mm)				do { } while (0)

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#define flush_cache_dup_mm(mm)				do { } while (0)

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#define flush_cache_range(vma, start, end)		do { } while (0)

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#define flush_cache_page(vma, vmaddr, pfn)		do { } while (0)

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#define flush_cache_vmap(start, end)			do { } while (0)

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#define flush_cache_vunmap(start, end)			do { } while (0)

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#define flush_icache_user_page(vma, page, addr, len)	do { } while (0)

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#define flush_dcache_mmap_lock(mapping)			do { } while (0)

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#define flush_dcache_mmap_unlock(mapping)		do { } while (0)

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#define cache_op(op, addr)						\

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	__asm__ __volatile__(						\

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	"	cacop	%0, %1					\n"	\

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	:								\

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	: "i" (op), "ZC" (*(unsigned char *)(addr)))

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static inline void flush_cache_line(int leaf, unsigned long addr)

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{

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	switch (leaf) {

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	case Cache_LEAF0:

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		cache_op(Index_Writeback_Inv_LEAF0, addr);

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		break;

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	case Cache_LEAF1:

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		cache_op(Index_Writeback_Inv_LEAF1, addr);

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		break;

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	case Cache_LEAF2:

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		cache_op(Index_Writeback_Inv_LEAF2, addr);

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		break;

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	case Cache_LEAF3:

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		cache_op(Index_Writeback_Inv_LEAF3, addr);

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		break;

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	case Cache_LEAF4:

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		cache_op(Index_Writeback_Inv_LEAF4, addr);

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		break;

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	case Cache_LEAF5:

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		cache_op(Index_Writeback_Inv_LEAF5, addr);

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		break;

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	default:

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		break;

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	}

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}

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#include <asm-generic/cacheflush.h>

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#endif /* _ASM_CACHEFLUSH_H */

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