Path: blob/master/arch/loongarch/include/asm/cpu-info.h
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/* SPDX-License-Identifier: GPL-2.0 */1/*2* Copyright (C) 2020-2022 Loongson Technology Corporation Limited3*/4#ifndef __ASM_CPU_INFO_H5#define __ASM_CPU_INFO_H67#include <linux/cache.h>8#include <linux/types.h>910#include <asm/loongarch.h>1112/* cache_desc->flags */13enum {14CACHE_PRESENT = (1 << 0),15CACHE_PRIVATE = (1 << 1), /* core private cache */16CACHE_INCLUSIVE = (1 << 2), /* include the inner level caches */17};1819/*20* Descriptor for a cache21*/22struct cache_desc {23unsigned char type;24unsigned char level;25unsigned short sets; /* Number of lines per set */26unsigned char ways; /* Number of ways */27unsigned char linesz; /* Size of line in bytes */28unsigned char flags; /* Flags describing cache properties */29};3031#define CACHE_LEVEL_MAX 332#define CACHE_LEAVES_MAX 63334struct cpuinfo_loongarch {35u64 asid_cache;36unsigned long asid_mask;3738/*39* Capability and feature descriptor structure for LoongArch CPU40*/41unsigned long long options;42unsigned int processor_id;43unsigned int fpu_vers;44unsigned int fpu_csr0;45unsigned int fpu_mask;46unsigned int cputype;47int isa_level;48int tlbsize;49int tlbsizemtlb;50int tlbsizestlbsets;51int tlbsizestlbways;52int cache_leaves_present; /* number of cache_leaves[] elements */53struct cache_desc cache_leaves[CACHE_LEAVES_MAX];54int core; /* physical core number in package */55int package;/* physical package number */56int global_id; /* physical global thread number */57int vabits; /* Virtual Address size in bits */58int pabits; /* Physical Address size in bits */59int timerbits; /* Width of arch timer in bits */60unsigned int ksave_mask; /* Usable KSave mask. */61unsigned int watch_dreg_count; /* Number data breakpoints */62unsigned int watch_ireg_count; /* Number instruction breakpoints */63unsigned int watch_reg_use_cnt; /* min(NUM_WATCH_REGS, watch_dreg_count + watch_ireg_count), Usable by ptrace */64} __aligned(SMP_CACHE_BYTES);6566extern struct cpuinfo_loongarch cpu_data[];67#define boot_cpu_data cpu_data[0]68#define current_cpu_data cpu_data[smp_processor_id()]69#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]7071extern void cpu_probe(void);7273extern const char *__cpu_family[];74extern const char *__cpu_full_name[];75#define cpu_family_string() __cpu_family[raw_smp_processor_id()]76#define cpu_full_name_string() __cpu_full_name[raw_smp_processor_id()]7778static inline bool cpus_are_siblings(int cpua, int cpub)79{80struct cpuinfo_loongarch *infoa = &cpu_data[cpua];81struct cpuinfo_loongarch *infob = &cpu_data[cpub];8283if (infoa->package != infob->package)84return false;8586if (infoa->core != infob->core)87return false;8889return true;90}9192static inline unsigned long cpu_asid_mask(struct cpuinfo_loongarch *cpuinfo)93{94return cpuinfo->asid_mask;95}9697static inline void set_cpu_asid_mask(struct cpuinfo_loongarch *cpuinfo,98unsigned long asid_mask)99{100cpuinfo->asid_mask = asid_mask;101}102103#endif /* __ASM_CPU_INFO_H */104105106