Path: blob/master/arch/loongarch/include/asm/fpregdef.h
26488 views
/* SPDX-License-Identifier: GPL-2.0 */1/*2* Definitions for the FPU register names3*4* Copyright (C) 2020-2022 Loongson Technology Corporation Limited5*/6#ifndef _ASM_FPREGDEF_H7#define _ASM_FPREGDEF_H89#define fa0 $f0 /* argument registers, fa0/fa1 reused as fv0/fv1 for return value */10#define fa1 $f111#define fa2 $f212#define fa3 $f313#define fa4 $f414#define fa5 $f515#define fa6 $f616#define fa7 $f717#define ft0 $f8 /* caller saved */18#define ft1 $f919#define ft2 $f1020#define ft3 $f1121#define ft4 $f1222#define ft5 $f1323#define ft6 $f1424#define ft7 $f1525#define ft8 $f1626#define ft9 $f1727#define ft10 $f1828#define ft11 $f1929#define ft12 $f2030#define ft13 $f2131#define ft14 $f2232#define ft15 $f2333#define fs0 $f24 /* callee saved */34#define fs1 $f2535#define fs2 $f2636#define fs3 $f2737#define fs4 $f2838#define fs5 $f2939#define fs6 $f3040#define fs7 $f314142#ifndef CONFIG_AS_HAS_FCSR_CLASS43/*44* Current binutils expects *GPRs* at FCSR position for the FCSR45* operation instructions, so define aliases for those used.46*/47#define fcsr0 $r048#define fcsr1 $r149#define fcsr2 $r250#define fcsr3 $r351#else52#define fcsr0 $fcsr053#define fcsr1 $fcsr154#define fcsr2 $fcsr255#define fcsr3 $fcsr356#endif5758#endif /* _ASM_FPREGDEF_H */596061