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torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/arch/m68k/coldfire/m5249.c
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// SPDX-License-Identifier: GPL-2.0

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/***************************************************************************/

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/*

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 *	m5249.c  -- platform support for ColdFire 5249 based boards

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 *

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 *	Copyright (C) 2002, Greg Ungerer ([email protected])

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 */

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/***************************************************************************/

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#include <linux/clkdev.h>

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#include <linux/kernel.h>

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#include <linux/param.h>

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#include <linux/init.h>

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#include <linux/io.h>

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#include <linux/platform_device.h>

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#include <asm/machdep.h>

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#include <asm/coldfire.h>

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#include <asm/mcfsim.h>

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#include <asm/mcfclk.h>

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/***************************************************************************/

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DEFINE_CLK(pll, "pll.0", MCF_CLK);

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DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);

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struct clk_lookup m5249_clk_lookup[] = {

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	CLKDEV_INIT(NULL, "pll.0", &clk_pll),

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	CLKDEV_INIT(NULL, "sys.0", &clk_sys),

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	CLKDEV_INIT("mcftmr.0", NULL, &clk_sys),

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	CLKDEV_INIT("mcftmr.1", NULL, &clk_sys),

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	CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),

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	CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),

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	CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys),

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	CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),

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	CLKDEV_INIT("imx1-i2c.1", NULL, &clk_sys),

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};

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/***************************************************************************/

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#ifdef CONFIG_M5249C3

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static struct resource m5249_smc91x_resources[] = {

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	{

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		.start		= 0xe0000300,

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		.end		= 0xe0000300 + 0x100,

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		.flags		= IORESOURCE_MEM,

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	},

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	{

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		.start		= MCF_IRQ_GPIO6,

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		.end		= MCF_IRQ_GPIO6,

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		.flags		= IORESOURCE_IRQ,

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	},

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};

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static struct platform_device m5249_smc91x = {

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	.name			= "smc91x",

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	.id			= 0,

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	.num_resources		= ARRAY_SIZE(m5249_smc91x_resources),

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	.resource		= m5249_smc91x_resources,

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};

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#endif /* CONFIG_M5249C3 */

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static struct platform_device *m5249_devices[] __initdata = {

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#ifdef CONFIG_M5249C3

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	&m5249_smc91x,

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#endif

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};

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/***************************************************************************/

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static void __init m5249_qspi_init(void)

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{

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#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)

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	/* QSPI irq setup */

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	writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,

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	       MCFSIM_QSPIICR);

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	mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);

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#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */

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}

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/***************************************************************************/

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static void __init m5249_i2c_init(void)

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{

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#if IS_ENABLED(CONFIG_I2C_IMX)

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	u32 r;

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	/* first I2C controller uses regular irq setup */

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	writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,

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	       MCFSIM_I2CICR);

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	mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);

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	/* second I2C controller is completely different */

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	r = readl(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));

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	r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1);

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	r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1);

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	writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));

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#endif /* CONFIG_I2C_IMX */

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}

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/***************************************************************************/

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#ifdef CONFIG_M5249C3

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static void __init m5249_smc91x_init(void)

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{

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	u32  gpio;

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	/* Set the GPIO line as interrupt source for smc91x device */

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	gpio = readl(MCFSIM2_GPIOINTENABLE);

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	writel(gpio | 0x40, MCFSIM2_GPIOINTENABLE);

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	gpio = readl(MCFINTC2_INTPRI5);

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	writel(gpio | 0x04000000, MCFINTC2_INTPRI5);

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}

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#endif /* CONFIG_M5249C3 */

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/***************************************************************************/

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void __init config_BSP(char *commandp, int size)

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{

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	mach_sched_init = hw_timer_init;

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#ifdef CONFIG_M5249C3

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	m5249_smc91x_init();

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#endif

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	m5249_qspi_init();

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	m5249_i2c_init();

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	clkdev_add_table(m5249_clk_lookup, ARRAY_SIZE(m5249_clk_lookup));

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}

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/***************************************************************************/

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static int __init init_BSP(void)

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{

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	platform_add_devices(m5249_devices, ARRAY_SIZE(m5249_devices));

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	return 0;

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}

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arch_initcall(init_BSP);

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/***************************************************************************/

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