Path: blob/master/arch/microblaze/include/asm/exceptions.h
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/* SPDX-License-Identifier: GPL-2.0 */1/*2* Preliminary support for HW exception handing for Microblaze3*4* Copyright (C) 2008-2009 Michal Simek <[email protected]>5* Copyright (C) 2008-2009 PetaLogix6* Copyright (C) 2005 John Williams <[email protected]>7*/89#ifndef _ASM_MICROBLAZE_EXCEPTIONS_H10#define _ASM_MICROBLAZE_EXCEPTIONS_H1112#ifdef __KERNEL__13#ifndef __ASSEMBLY__1415/* Macros to enable and disable HW exceptions in the MSR */16/* Define MSR enable bit for HW exceptions */17#define HWEX_MSR_BIT (1 << 8)1819#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR20#define __enable_hw_exceptions() \21__asm__ __volatile__ (" msrset r0, %0; \22nop;" \23: \24: "i" (HWEX_MSR_BIT) \25: "memory")2627#define __disable_hw_exceptions() \28__asm__ __volatile__ (" msrclr r0, %0; \29nop;" \30: \31: "i" (HWEX_MSR_BIT) \32: "memory")33#else /* !CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR */34#define __enable_hw_exceptions() \35__asm__ __volatile__ (" \36mfs r12, rmsr; \37nop; \38ori r12, r12, %0; \39mts rmsr, r12; \40nop;" \41: \42: "i" (HWEX_MSR_BIT) \43: "memory", "r12")4445#define __disable_hw_exceptions() \46__asm__ __volatile__ (" \47mfs r12, rmsr; \48nop; \49andi r12, r12, ~%0; \50mts rmsr, r12; \51nop;" \52: \53: "i" (HWEX_MSR_BIT) \54: "memory", "r12")55#endif /* CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR */5657asmlinkage void full_exception(struct pt_regs *regs, unsigned int type,58int fsr, int addr);5960asmlinkage void sw_exception(struct pt_regs *regs);61void bad_page_fault(struct pt_regs *regs, unsigned long address, int sig);6263void die(const char *str, struct pt_regs *fp, long err);64void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr);6566#endif /*__ASSEMBLY__ */67#endif /* __KERNEL__ */68#endif /* _ASM_MICROBLAZE_EXCEPTIONS_H */697071