Path: blob/master/arch/microblaze/include/asm/pci-bridge.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */1#ifndef _ASM_MICROBLAZE_PCI_BRIDGE_H2#define _ASM_MICROBLAZE_PCI_BRIDGE_H3#ifdef __KERNEL__4/*5*/6#include <linux/pci.h>7#include <linux/list.h>8#include <linux/ioport.h>910struct device_node;1112#ifdef CONFIG_PCI13extern struct list_head hose_list;14extern int pcibios_vaddr_is_ioport(void __iomem *address);15#else16static inline int pcibios_vaddr_is_ioport(void __iomem *address)17{18return 0;19}20#endif2122/*23* Structure of a PCI controller (host bridge)24*/25struct pci_controller {26struct pci_bus *bus;27struct list_head list_node;2829void __iomem *io_base_virt;3031/* Currently, we limit ourselves to 1 IO range and 3 mem32* ranges since the common pci_bus structure can't handle more33*/34struct resource io_resource;35};3637#ifdef CONFIG_PCI38static inline int isa_vaddr_is_ioport(void __iomem *address)39{40/* No specific ISA handling on ppc32 at this stage, it41* all goes through PCI42*/43return 0;44}45#endif /* CONFIG_PCI */4647#endif /* __KERNEL__ */48#endif /* _ASM_MICROBLAZE_PCI_BRIDGE_H */495051