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torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/arch/mips/ath79/common.c
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// SPDX-License-Identifier: GPL-2.0-only

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/*

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 *  Atheros AR71XX/AR724X/AR913X common routines

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 *

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 *  Copyright (C) 2010-2011 Jaiganesh Narayanan <[email protected]>

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 *  Copyright (C) 2008-2011 Gabor Juhos <[email protected]>

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 *  Copyright (C) 2008 Imre Kaloz <[email protected]>

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 *

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 *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP

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 */

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#include <linux/kernel.h>

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#include <linux/export.h>

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#include <linux/types.h>

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#include <linux/spinlock.h>

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#include <asm/mach-ath79/ath79.h>

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#include <asm/mach-ath79/ar71xx_regs.h>

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#include "common.h"

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static DEFINE_SPINLOCK(ath79_device_reset_lock);

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u32 ath79_cpu_freq;

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EXPORT_SYMBOL_GPL(ath79_cpu_freq);

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u32 ath79_ahb_freq;

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EXPORT_SYMBOL_GPL(ath79_ahb_freq);

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u32 ath79_ddr_freq;

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EXPORT_SYMBOL_GPL(ath79_ddr_freq);

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enum ath79_soc_type ath79_soc;

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unsigned int ath79_soc_rev;

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void __iomem *ath79_pll_base;

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void __iomem *ath79_reset_base;

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EXPORT_SYMBOL_GPL(ath79_reset_base);

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static void __iomem *ath79_ddr_base;

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static void __iomem *ath79_ddr_wb_flush_base;

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static void __iomem *ath79_ddr_pci_win_base;

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void ath79_ddr_ctrl_init(void)

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{

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	ath79_ddr_base = ioremap(AR71XX_DDR_CTRL_BASE,

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					 AR71XX_DDR_CTRL_SIZE);

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	if (soc_is_ar913x() || soc_is_ar724x() || soc_is_ar933x()) {

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		ath79_ddr_wb_flush_base = ath79_ddr_base + 0x7c;

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		ath79_ddr_pci_win_base = 0;

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	} else {

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		ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c;

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		ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c;

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	}

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}

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EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init);

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void ath79_ddr_wb_flush(u32 reg)

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{

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	void __iomem *flush_reg = ath79_ddr_wb_flush_base + (reg * 4);

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	/* Flush the DDR write buffer. */

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	__raw_writel(0x1, flush_reg);

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	while (__raw_readl(flush_reg) & 0x1)

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		;

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	/* It must be run twice. */

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	__raw_writel(0x1, flush_reg);

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	while (__raw_readl(flush_reg) & 0x1)

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		;

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}

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EXPORT_SYMBOL_GPL(ath79_ddr_wb_flush);

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void ath79_ddr_set_pci_windows(void)

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{

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	BUG_ON(!ath79_ddr_pci_win_base);

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	__raw_writel(AR71XX_PCI_WIN0_OFFS, ath79_ddr_pci_win_base + 0x0);

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	__raw_writel(AR71XX_PCI_WIN1_OFFS, ath79_ddr_pci_win_base + 0x4);

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	__raw_writel(AR71XX_PCI_WIN2_OFFS, ath79_ddr_pci_win_base + 0x8);

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	__raw_writel(AR71XX_PCI_WIN3_OFFS, ath79_ddr_pci_win_base + 0xc);

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	__raw_writel(AR71XX_PCI_WIN4_OFFS, ath79_ddr_pci_win_base + 0x10);

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	__raw_writel(AR71XX_PCI_WIN5_OFFS, ath79_ddr_pci_win_base + 0x14);

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	__raw_writel(AR71XX_PCI_WIN6_OFFS, ath79_ddr_pci_win_base + 0x18);

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	__raw_writel(AR71XX_PCI_WIN7_OFFS, ath79_ddr_pci_win_base + 0x1c);

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}

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EXPORT_SYMBOL_GPL(ath79_ddr_set_pci_windows);

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void ath79_device_reset_set(u32 mask)

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{

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	unsigned long flags;

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	u32 reg;

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	u32 t;

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	if (soc_is_ar71xx())

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		reg = AR71XX_RESET_REG_RESET_MODULE;

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	else if (soc_is_ar724x())

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		reg = AR724X_RESET_REG_RESET_MODULE;

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	else if (soc_is_ar913x())

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		reg = AR913X_RESET_REG_RESET_MODULE;

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	else if (soc_is_ar933x())

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		reg = AR933X_RESET_REG_RESET_MODULE;

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	else if (soc_is_ar934x())

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		reg = AR934X_RESET_REG_RESET_MODULE;

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	else if (soc_is_qca953x())

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		reg = QCA953X_RESET_REG_RESET_MODULE;

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	else if (soc_is_qca955x())

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		reg = QCA955X_RESET_REG_RESET_MODULE;

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	else if (soc_is_qca956x() || soc_is_tp9343())

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		reg = QCA956X_RESET_REG_RESET_MODULE;

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	else

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		BUG();

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	spin_lock_irqsave(&ath79_device_reset_lock, flags);

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	t = ath79_reset_rr(reg);

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	ath79_reset_wr(reg, t | mask);

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	spin_unlock_irqrestore(&ath79_device_reset_lock, flags);

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}

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EXPORT_SYMBOL_GPL(ath79_device_reset_set);

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void ath79_device_reset_clear(u32 mask)

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{

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	unsigned long flags;

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	u32 reg;

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	u32 t;

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	if (soc_is_ar71xx())

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		reg = AR71XX_RESET_REG_RESET_MODULE;

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	else if (soc_is_ar724x())

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		reg = AR724X_RESET_REG_RESET_MODULE;

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	else if (soc_is_ar913x())

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		reg = AR913X_RESET_REG_RESET_MODULE;

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	else if (soc_is_ar933x())

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		reg = AR933X_RESET_REG_RESET_MODULE;

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	else if (soc_is_ar934x())

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		reg = AR934X_RESET_REG_RESET_MODULE;

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	else if (soc_is_qca953x())

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		reg = QCA953X_RESET_REG_RESET_MODULE;

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	else if (soc_is_qca955x())

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		reg = QCA955X_RESET_REG_RESET_MODULE;

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	else if (soc_is_qca956x() || soc_is_tp9343())

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		reg = QCA956X_RESET_REG_RESET_MODULE;

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	else

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		BUG();

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	spin_lock_irqsave(&ath79_device_reset_lock, flags);

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	t = ath79_reset_rr(reg);

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	ath79_reset_wr(reg, t & ~mask);

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	spin_unlock_irqrestore(&ath79_device_reset_lock, flags);

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}

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EXPORT_SYMBOL_GPL(ath79_device_reset_clear);

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