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torvalds
GitHub Repository: torvalds/linux
Path: blob/master/arch/mips/fw/cfe/cfe_api.c
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2000, 2001, 2002 Broadcom Corporation
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*/
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/*
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*
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* Broadcom Common Firmware Environment (CFE)
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*
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* This module contains device function stubs (small routines to
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* call the standard "iocb" interface entry point to CFE).
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* There should be one routine here per iocb function call.
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*
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* Authors: Mitch Lichtenberg, Chris Demetriou
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/printk.h>
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#include <asm/mipsregs.h>
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#include <asm/fw/cfe/cfe_api.h>
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#include "cfe_api_int.h"
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unsigned long __initdata cfe_seal;
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/* Cast from a native pointer to a cfe_xptr_t and back. */
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#define XPTR_FROM_NATIVE(n) ((cfe_xptr_t) (intptr_t) (n))
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#define NATIVE_FROM_XPTR(x) ((void *) (intptr_t) (x))
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int cfe_iocb_dispatch(struct cfe_xiocb *xiocb);
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/*
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* Declare the dispatch function with args of "intptr_t".
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* This makes sure whatever model we're compiling in
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* puts the pointers in a single register. For example,
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* combining -mlong64 and -mips1 or -mips2 would lead to
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* trouble, since the handle and IOCB pointer will be
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* passed in two registers each, and CFE expects one.
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*/
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static int (*cfe_dispfunc) (intptr_t handle, intptr_t xiocb);
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static u64 cfe_handle;
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int cfe_init(u64 handle, u64 ept)
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{
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cfe_dispfunc = NATIVE_FROM_XPTR(ept);
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cfe_handle = handle;
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return 0;
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}
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int cfe_iocb_dispatch(struct cfe_xiocb * xiocb)
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{
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if (!cfe_dispfunc)
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return -1;
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return (*cfe_dispfunc) ((intptr_t) cfe_handle, (intptr_t) xiocb);
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}
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int cfe_close(int handle)
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{
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struct cfe_xiocb xiocb;
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xiocb.xiocb_fcode = CFE_CMD_DEV_CLOSE;
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xiocb.xiocb_status = 0;
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xiocb.xiocb_handle = handle;
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xiocb.xiocb_flags = 0;
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xiocb.xiocb_psize = 0;
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cfe_iocb_dispatch(&xiocb);
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return xiocb.xiocb_status;
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}
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int cfe_cpu_start(int cpu, void (*fn) (void), long sp, long gp, long a1)
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{
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struct cfe_xiocb xiocb;
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xiocb.xiocb_fcode = CFE_CMD_FW_CPUCTL;
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xiocb.xiocb_status = 0;
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xiocb.xiocb_handle = 0;
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xiocb.xiocb_flags = 0;
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xiocb.xiocb_psize = sizeof(struct xiocb_cpuctl);
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xiocb.plist.xiocb_cpuctl.cpu_number = cpu;
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xiocb.plist.xiocb_cpuctl.cpu_command = CFE_CPU_CMD_START;
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xiocb.plist.xiocb_cpuctl.gp_val = gp;
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xiocb.plist.xiocb_cpuctl.sp_val = sp;
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xiocb.plist.xiocb_cpuctl.a1_val = a1;
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xiocb.plist.xiocb_cpuctl.start_addr = (long) fn;
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cfe_iocb_dispatch(&xiocb);
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return xiocb.xiocb_status;
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}
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int cfe_cpu_stop(int cpu)
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{
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struct cfe_xiocb xiocb;
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xiocb.xiocb_fcode = CFE_CMD_FW_CPUCTL;
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xiocb.xiocb_status = 0;
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xiocb.xiocb_handle = 0;
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xiocb.xiocb_flags = 0;
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xiocb.xiocb_psize = sizeof(struct xiocb_cpuctl);
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xiocb.plist.xiocb_cpuctl.cpu_number = cpu;
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xiocb.plist.xiocb_cpuctl.cpu_command = CFE_CPU_CMD_STOP;
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cfe_iocb_dispatch(&xiocb);
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return xiocb.xiocb_status;
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}
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int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen)
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{
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struct cfe_xiocb xiocb;
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xiocb.xiocb_fcode = CFE_CMD_ENV_SET;
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xiocb.xiocb_status = 0;
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xiocb.xiocb_handle = 0;
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xiocb.xiocb_flags = 0;
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xiocb.xiocb_psize = sizeof(struct xiocb_envbuf);
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xiocb.plist.xiocb_envbuf.enum_idx = idx;
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xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name);
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xiocb.plist.xiocb_envbuf.name_length = namelen;
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xiocb.plist.xiocb_envbuf.val_ptr = XPTR_FROM_NATIVE(val);
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xiocb.plist.xiocb_envbuf.val_length = vallen;
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cfe_iocb_dispatch(&xiocb);
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return xiocb.xiocb_status;
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}
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int
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cfe_enummem(int idx, int flags, u64 *start, u64 *length, u64 *type)
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{
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struct cfe_xiocb xiocb;
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xiocb.xiocb_fcode = CFE_CMD_FW_MEMENUM;
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xiocb.xiocb_status = 0;
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xiocb.xiocb_handle = 0;
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xiocb.xiocb_flags = flags;
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xiocb.xiocb_psize = sizeof(struct xiocb_meminfo);
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xiocb.plist.xiocb_meminfo.mi_idx = idx;
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cfe_iocb_dispatch(&xiocb);
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if (xiocb.xiocb_status < 0)
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return xiocb.xiocb_status;
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*start = xiocb.plist.xiocb_meminfo.mi_addr;
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*length = xiocb.plist.xiocb_meminfo.mi_size;
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*type = xiocb.plist.xiocb_meminfo.mi_type;
151
152
return 0;
153
}
154
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int cfe_exit(int warm, int status)
156
{
157
struct cfe_xiocb xiocb;
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159
xiocb.xiocb_fcode = CFE_CMD_FW_RESTART;
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xiocb.xiocb_status = 0;
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xiocb.xiocb_handle = 0;
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xiocb.xiocb_flags = warm ? CFE_FLG_WARMSTART : 0;
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xiocb.xiocb_psize = sizeof(struct xiocb_exitstat);
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xiocb.plist.xiocb_exitstat.status = status;
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cfe_iocb_dispatch(&xiocb);
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return xiocb.xiocb_status;
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}
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int cfe_flushcache(int flg)
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{
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struct cfe_xiocb xiocb;
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xiocb.xiocb_fcode = CFE_CMD_FW_FLUSHCACHE;
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xiocb.xiocb_status = 0;
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xiocb.xiocb_handle = 0;
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xiocb.xiocb_flags = flg;
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xiocb.xiocb_psize = 0;
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cfe_iocb_dispatch(&xiocb);
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return xiocb.xiocb_status;
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}
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int cfe_getdevinfo(char *name)
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{
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struct cfe_xiocb xiocb;
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xiocb.xiocb_fcode = CFE_CMD_DEV_GETINFO;
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xiocb.xiocb_status = 0;
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xiocb.xiocb_handle = 0;
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xiocb.xiocb_flags = 0;
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xiocb.xiocb_psize = sizeof(struct xiocb_buffer);
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xiocb.plist.xiocb_buffer.buf_offset = 0;
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xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(name);
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xiocb.plist.xiocb_buffer.buf_length = strlen(name);
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cfe_iocb_dispatch(&xiocb);
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if (xiocb.xiocb_status < 0)
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return xiocb.xiocb_status;
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return xiocb.plist.xiocb_buffer.buf_ioctlcmd;
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}
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int cfe_getenv(char *name, char *dest, int destlen)
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{
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struct cfe_xiocb xiocb;
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*dest = 0;
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xiocb.xiocb_fcode = CFE_CMD_ENV_GET;
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xiocb.xiocb_status = 0;
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xiocb.xiocb_handle = 0;
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xiocb.xiocb_flags = 0;
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xiocb.xiocb_psize = sizeof(struct xiocb_envbuf);
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xiocb.plist.xiocb_envbuf.enum_idx = 0;
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xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name);
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xiocb.plist.xiocb_envbuf.name_length = strlen(name);
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xiocb.plist.xiocb_envbuf.val_ptr = XPTR_FROM_NATIVE(dest);
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xiocb.plist.xiocb_envbuf.val_length = destlen;
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cfe_iocb_dispatch(&xiocb);
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return xiocb.xiocb_status;
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}
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int cfe_getfwinfo(cfe_fwinfo_t * info)
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{
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struct cfe_xiocb xiocb;
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xiocb.xiocb_fcode = CFE_CMD_FW_GETINFO;
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xiocb.xiocb_status = 0;
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xiocb.xiocb_handle = 0;
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xiocb.xiocb_flags = 0;
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xiocb.xiocb_psize = sizeof(struct xiocb_fwinfo);
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cfe_iocb_dispatch(&xiocb);
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if (xiocb.xiocb_status < 0)
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return xiocb.xiocb_status;
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info->fwi_version = xiocb.plist.xiocb_fwinfo.fwi_version;
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info->fwi_totalmem = xiocb.plist.xiocb_fwinfo.fwi_totalmem;
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info->fwi_flags = xiocb.plist.xiocb_fwinfo.fwi_flags;
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info->fwi_boardid = xiocb.plist.xiocb_fwinfo.fwi_boardid;
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info->fwi_bootarea_va = xiocb.plist.xiocb_fwinfo.fwi_bootarea_va;
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info->fwi_bootarea_pa = xiocb.plist.xiocb_fwinfo.fwi_bootarea_pa;
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info->fwi_bootarea_size =
250
xiocb.plist.xiocb_fwinfo.fwi_bootarea_size;
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return 0;
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}
254
255
int cfe_getstdhandle(int flg)
256
{
257
struct cfe_xiocb xiocb;
258
259
xiocb.xiocb_fcode = CFE_CMD_DEV_GETHANDLE;
260
xiocb.xiocb_status = 0;
261
xiocb.xiocb_handle = 0;
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xiocb.xiocb_flags = flg;
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xiocb.xiocb_psize = 0;
264
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cfe_iocb_dispatch(&xiocb);
266
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if (xiocb.xiocb_status < 0)
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return xiocb.xiocb_status;
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return xiocb.xiocb_handle;
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}
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int64_t
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cfe_getticks(void)
274
{
275
struct cfe_xiocb xiocb;
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xiocb.xiocb_fcode = CFE_CMD_FW_GETTIME;
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xiocb.xiocb_status = 0;
279
xiocb.xiocb_handle = 0;
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xiocb.xiocb_flags = 0;
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xiocb.xiocb_psize = sizeof(struct xiocb_time);
282
xiocb.plist.xiocb_time.ticks = 0;
283
284
cfe_iocb_dispatch(&xiocb);
285
286
return xiocb.plist.xiocb_time.ticks;
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}
289
290
int cfe_inpstat(int handle)
291
{
292
struct cfe_xiocb xiocb;
293
294
xiocb.xiocb_fcode = CFE_CMD_DEV_INPSTAT;
295
xiocb.xiocb_status = 0;
296
xiocb.xiocb_handle = handle;
297
xiocb.xiocb_flags = 0;
298
xiocb.xiocb_psize = sizeof(struct xiocb_inpstat);
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xiocb.plist.xiocb_inpstat.inp_status = 0;
300
301
cfe_iocb_dispatch(&xiocb);
302
303
if (xiocb.xiocb_status < 0)
304
return xiocb.xiocb_status;
305
return xiocb.plist.xiocb_inpstat.inp_status;
306
}
307
308
int
309
cfe_ioctl(int handle, unsigned int ioctlnum, unsigned char *buffer,
310
int length, int *retlen, u64 offset)
311
{
312
struct cfe_xiocb xiocb;
313
314
xiocb.xiocb_fcode = CFE_CMD_DEV_IOCTL;
315
xiocb.xiocb_status = 0;
316
xiocb.xiocb_handle = handle;
317
xiocb.xiocb_flags = 0;
318
xiocb.xiocb_psize = sizeof(struct xiocb_buffer);
319
xiocb.plist.xiocb_buffer.buf_offset = offset;
320
xiocb.plist.xiocb_buffer.buf_ioctlcmd = ioctlnum;
321
xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer);
322
xiocb.plist.xiocb_buffer.buf_length = length;
323
324
cfe_iocb_dispatch(&xiocb);
325
326
if (retlen)
327
*retlen = xiocb.plist.xiocb_buffer.buf_retlen;
328
return xiocb.xiocb_status;
329
}
330
331
int cfe_open(char *name)
332
{
333
struct cfe_xiocb xiocb;
334
335
xiocb.xiocb_fcode = CFE_CMD_DEV_OPEN;
336
xiocb.xiocb_status = 0;
337
xiocb.xiocb_handle = 0;
338
xiocb.xiocb_flags = 0;
339
xiocb.xiocb_psize = sizeof(struct xiocb_buffer);
340
xiocb.plist.xiocb_buffer.buf_offset = 0;
341
xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(name);
342
xiocb.plist.xiocb_buffer.buf_length = strlen(name);
343
344
cfe_iocb_dispatch(&xiocb);
345
346
if (xiocb.xiocb_status < 0)
347
return xiocb.xiocb_status;
348
return xiocb.xiocb_handle;
349
}
350
351
int cfe_read(int handle, unsigned char *buffer, int length)
352
{
353
return cfe_readblk(handle, 0, buffer, length);
354
}
355
356
int cfe_readblk(int handle, s64 offset, unsigned char *buffer, int length)
357
{
358
struct cfe_xiocb xiocb;
359
360
xiocb.xiocb_fcode = CFE_CMD_DEV_READ;
361
xiocb.xiocb_status = 0;
362
xiocb.xiocb_handle = handle;
363
xiocb.xiocb_flags = 0;
364
xiocb.xiocb_psize = sizeof(struct xiocb_buffer);
365
xiocb.plist.xiocb_buffer.buf_offset = offset;
366
xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer);
367
xiocb.plist.xiocb_buffer.buf_length = length;
368
369
cfe_iocb_dispatch(&xiocb);
370
371
if (xiocb.xiocb_status < 0)
372
return xiocb.xiocb_status;
373
return xiocb.plist.xiocb_buffer.buf_retlen;
374
}
375
376
int cfe_setenv(char *name, char *val)
377
{
378
struct cfe_xiocb xiocb;
379
380
xiocb.xiocb_fcode = CFE_CMD_ENV_SET;
381
xiocb.xiocb_status = 0;
382
xiocb.xiocb_handle = 0;
383
xiocb.xiocb_flags = 0;
384
xiocb.xiocb_psize = sizeof(struct xiocb_envbuf);
385
xiocb.plist.xiocb_envbuf.enum_idx = 0;
386
xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name);
387
xiocb.plist.xiocb_envbuf.name_length = strlen(name);
388
xiocb.plist.xiocb_envbuf.val_ptr = XPTR_FROM_NATIVE(val);
389
xiocb.plist.xiocb_envbuf.val_length = strlen(val);
390
391
cfe_iocb_dispatch(&xiocb);
392
393
return xiocb.xiocb_status;
394
}
395
396
int cfe_write(int handle, const char *buffer, int length)
397
{
398
return cfe_writeblk(handle, 0, buffer, length);
399
}
400
401
int cfe_writeblk(int handle, s64 offset, const char *buffer, int length)
402
{
403
struct cfe_xiocb xiocb;
404
405
xiocb.xiocb_fcode = CFE_CMD_DEV_WRITE;
406
xiocb.xiocb_status = 0;
407
xiocb.xiocb_handle = handle;
408
xiocb.xiocb_flags = 0;
409
xiocb.xiocb_psize = sizeof(struct xiocb_buffer);
410
xiocb.plist.xiocb_buffer.buf_offset = offset;
411
xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer);
412
xiocb.plist.xiocb_buffer.buf_length = length;
413
414
cfe_iocb_dispatch(&xiocb);
415
416
if (xiocb.xiocb_status < 0)
417
return xiocb.xiocb_status;
418
return xiocb.plist.xiocb_buffer.buf_retlen;
419
}
420
421
void __init cfe_die(char *fmt, ...)
422
{
423
unsigned int prid, __maybe_unused rev;
424
char msg[128];
425
va_list ap;
426
int handle;
427
unsigned int count;
428
429
va_start(ap, fmt);
430
vsprintf(msg, fmt, ap);
431
strcat(msg, "\r\n");
432
433
if (cfe_seal != CFE_EPTSEAL)
434
goto no_cfe;
435
436
prid = read_c0_prid();
437
if ((prid & PRID_COMP_MASK) != PRID_COMP_BROADCOM)
438
goto no_cfe;
439
440
rev = prid & PRID_REV_MASK;
441
442
/* disable XKS01 so that CFE can access the registers */
443
switch (prid & PRID_IMP_MASK) {
444
#ifdef CONFIG_CPU_BMIPS4380
445
case PRID_IMP_BMIPS43XX:
446
if (rev >= PRID_REV_BMIPS4380_LO &&
447
rev <= PRID_REV_BMIPS4380_HI)
448
__write_32bit_c0_register($22, 3,
449
__read_32bit_c0_register($22, 3) & ~BIT(12));
450
break;
451
#endif
452
#ifdef CONFIG_CPU_BMIPS5000
453
case PRID_IMP_BMIPS5000:
454
case PRID_IMP_BMIPS5200:
455
__write_32bit_c0_register($22, 5,
456
__read_32bit_c0_register($22, 5) & ~BIT(8));
457
break;
458
#endif
459
default:
460
break;
461
}
462
463
handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
464
if (handle < 0)
465
goto no_cfe;
466
467
cfe_write(handle, msg, strlen(msg));
468
469
for (count = 0; count < 0x7fffffff; count++)
470
mb();
471
cfe_exit(0, 1);
472
while (1)
473
;
474
475
no_cfe:
476
/* probably won't print anywhere useful */
477
panic("%s", msg);
478
479
va_end(ap);
480
}
481
482