CoCalc -- asmmacro.h

GitHub Repository: torvalds/linux
Path: blob/master/arch/mips/include/asm/asmmacro.h
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/*
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 * This file is subject to the terms and conditions of the GNU General Public
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 * License.  See the file "COPYING" in the main directory of this archive
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 * for more details.
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 *
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 * Copyright (C) 2003 Ralf Baechle
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 */
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#ifndef _ASM_ASMMACRO_H
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#define _ASM_ASMMACRO_H
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#include <asm/hazards.h>
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#include <asm/asm-offsets.h>
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#include <asm/msa.h>
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#ifdef CONFIG_32BIT
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#include <asm/asmmacro-32.h>
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#endif
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#ifdef CONFIG_64BIT
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#include <asm/asmmacro-64.h>
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#endif
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/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
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#undef fp
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/*
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 * Helper macros for generating raw instruction encodings.
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 */
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#ifdef CONFIG_CPU_MICROMIPS
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	.macro	insn32_if_mm enc
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	.insn
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	.hword ((\enc) >> 16)
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	.hword ((\enc) & 0xffff)
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	.endm
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	.macro	insn_if_mips enc
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	.endm
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#else
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	.macro	insn32_if_mm enc
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	.endm
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	.macro	insn_if_mips enc
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	.insn
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	.word (\enc)
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	.endm
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#endif
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#ifdef CONFIG_CPU_HAS_DIEI
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	.macro	local_irq_enable
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	ei
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	irq_enable_hazard
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	.endm
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	.macro	local_irq_disable
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	di
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	irq_disable_hazard
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	.endm
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#else /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
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	.macro	local_irq_enable reg=t0
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	mfc0	\reg, CP0_STATUS
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	ori	\reg, \reg, 1
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	mtc0	\reg, CP0_STATUS
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	irq_enable_hazard
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	.endm
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	.macro	local_irq_disable reg=t0
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#ifdef CONFIG_PREEMPTION
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	lw      \reg, TI_PRE_COUNT($28)
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	addi    \reg, \reg, 1
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	sw      \reg, TI_PRE_COUNT($28)
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#endif
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	mfc0	\reg, CP0_STATUS
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	ori	\reg, \reg, 1
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	xori	\reg, \reg, 1
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	mtc0	\reg, CP0_STATUS
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	irq_disable_hazard
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#ifdef CONFIG_PREEMPTION
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	lw      \reg, TI_PRE_COUNT($28)
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	addi    \reg, \reg, -1
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	sw      \reg, TI_PRE_COUNT($28)
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#endif
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	.endm
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#endif  /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
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	.macro	fpu_save_16even thread tmp=t0
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	.set	push
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	.set	hardfloat
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	cfc1	\tmp, fcr31
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	sdc1	$f0,  THREAD_FPR0(\thread)
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	sdc1	$f2,  THREAD_FPR2(\thread)
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	sdc1	$f4,  THREAD_FPR4(\thread)
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	sdc1	$f6,  THREAD_FPR6(\thread)
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	sdc1	$f8,  THREAD_FPR8(\thread)
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	sdc1	$f10, THREAD_FPR10(\thread)
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	sdc1	$f12, THREAD_FPR12(\thread)
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	sdc1	$f14, THREAD_FPR14(\thread)
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	sdc1	$f16, THREAD_FPR16(\thread)
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	sdc1	$f18, THREAD_FPR18(\thread)
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	sdc1	$f20, THREAD_FPR20(\thread)
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	sdc1	$f22, THREAD_FPR22(\thread)
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	sdc1	$f24, THREAD_FPR24(\thread)
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	sdc1	$f26, THREAD_FPR26(\thread)
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	sdc1	$f28, THREAD_FPR28(\thread)
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	sdc1	$f30, THREAD_FPR30(\thread)
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	sw	\tmp, THREAD_FCR31(\thread)
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	.set	pop
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	.endm
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	.macro	fpu_save_16odd thread
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	.set	push
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	.set	mips64r2
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	.set	fp=64
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	.set	hardfloat
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	sdc1	$f1,  THREAD_FPR1(\thread)
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	sdc1	$f3,  THREAD_FPR3(\thread)
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	sdc1	$f5,  THREAD_FPR5(\thread)
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	sdc1	$f7,  THREAD_FPR7(\thread)
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	sdc1	$f9,  THREAD_FPR9(\thread)
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	sdc1	$f11, THREAD_FPR11(\thread)
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	sdc1	$f13, THREAD_FPR13(\thread)
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	sdc1	$f15, THREAD_FPR15(\thread)
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	sdc1	$f17, THREAD_FPR17(\thread)
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	sdc1	$f19, THREAD_FPR19(\thread)
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	sdc1	$f21, THREAD_FPR21(\thread)
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	sdc1	$f23, THREAD_FPR23(\thread)
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	sdc1	$f25, THREAD_FPR25(\thread)
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	sdc1	$f27, THREAD_FPR27(\thread)
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	sdc1	$f29, THREAD_FPR29(\thread)
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	sdc1	$f31, THREAD_FPR31(\thread)
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	.set	pop
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	.endm
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	.macro	fpu_save_double thread status tmp
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#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
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    defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
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	sll	\tmp, \status, 5
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	bgez	\tmp, 10f
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	fpu_save_16odd \thread
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10:
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#endif
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	fpu_save_16even \thread \tmp
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	.endm
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	.macro	fpu_restore_16even thread tmp=t0
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	.set	push
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	.set	hardfloat
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	lw	\tmp, THREAD_FCR31(\thread)
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	ldc1	$f0,  THREAD_FPR0(\thread)
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	ldc1	$f2,  THREAD_FPR2(\thread)
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	ldc1	$f4,  THREAD_FPR4(\thread)
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	ldc1	$f6,  THREAD_FPR6(\thread)
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	ldc1	$f8,  THREAD_FPR8(\thread)
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	ldc1	$f10, THREAD_FPR10(\thread)
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	ldc1	$f12, THREAD_FPR12(\thread)
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	ldc1	$f14, THREAD_FPR14(\thread)
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	ldc1	$f16, THREAD_FPR16(\thread)
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	ldc1	$f18, THREAD_FPR18(\thread)
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	ldc1	$f20, THREAD_FPR20(\thread)
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	ldc1	$f22, THREAD_FPR22(\thread)
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	ldc1	$f24, THREAD_FPR24(\thread)
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	ldc1	$f26, THREAD_FPR26(\thread)
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	ldc1	$f28, THREAD_FPR28(\thread)
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	ldc1	$f30, THREAD_FPR30(\thread)
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	ctc1	\tmp, fcr31
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	.set	pop
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	.endm
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	.macro	fpu_restore_16odd thread
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	.set	push
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	.set	mips64r2
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	.set	fp=64
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	.set	hardfloat
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	ldc1	$f1,  THREAD_FPR1(\thread)
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	ldc1	$f3,  THREAD_FPR3(\thread)
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	ldc1	$f5,  THREAD_FPR5(\thread)
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	ldc1	$f7,  THREAD_FPR7(\thread)
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	ldc1	$f9,  THREAD_FPR9(\thread)
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	ldc1	$f11, THREAD_FPR11(\thread)
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	ldc1	$f13, THREAD_FPR13(\thread)
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	ldc1	$f15, THREAD_FPR15(\thread)
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	ldc1	$f17, THREAD_FPR17(\thread)
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	ldc1	$f19, THREAD_FPR19(\thread)
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	ldc1	$f21, THREAD_FPR21(\thread)
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	ldc1	$f23, THREAD_FPR23(\thread)
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	ldc1	$f25, THREAD_FPR25(\thread)
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	ldc1	$f27, THREAD_FPR27(\thread)
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	ldc1	$f29, THREAD_FPR29(\thread)
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	ldc1	$f31, THREAD_FPR31(\thread)
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	.set	pop
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	.endm
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	.macro	fpu_restore_double thread status tmp
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#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
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    defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6)
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	sll	\tmp, \status, 5
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	bgez	\tmp, 10f				# 16 register mode?
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	fpu_restore_16odd \thread
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10:
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#endif
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	fpu_restore_16even \thread \tmp
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	.endm
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#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
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    defined(CONFIG_CPU_MIPSR6)
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	.macro	_EXT	rd, rs, p, s
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	ext	\rd, \rs, \p, \s
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	.endm
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#else /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
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	.macro	_EXT	rd, rs, p, s
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	srl	\rd, \rs, \p
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	andi	\rd, \rd, (1 << \s) - 1
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	.endm
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#endif /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */
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/*
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 * Temporary until all gas have MT ASE support
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 */
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	.macro	DMT	reg=0
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	insn_if_mips	0x41600bc1 | (\reg << 16)
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	insn32_if_mm    0x0000057C | (\reg << 21)
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	.endm
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	.macro	EMT	reg=0
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	insn_if_mips	0x41600be1 | (\reg << 16)
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	insn32_if_mm    0x0000257C | (\reg << 21)
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	.endm
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	.macro	DVPE	reg=0
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	insn_if_mips	0x41600001 | (\reg << 16)
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	insn32_if_mm    0x0000157C | (\reg << 21)
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	.endm
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	.macro	EVPE	reg=0
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	insn_if_mips	0x41600021 | (\reg << 16)
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	insn32_if_mm    0x0000357C | (\reg << 21)
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	.endm
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	.macro	MFTR	rs=0, rt=0, u=0, sel=0
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	insn_if_mips	0x41000000 | (\rt << 16) | (\rs << 11) | (\u << 5) | (\sel)
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	insn32_if_mm	0x0000000E | (\rt << 21) | (\rs << 16) | (\u << 10) | (\sel << 4)
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	.endm
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	.macro	MTTR	rt=0, rs=0, u=0, sel=0
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	insn_if_mips	0x41800000 | (\rt << 16) | (\rs << 11) | (\u << 5) | (\sel)
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	insn32_if_mm	0x00000006 | (\rt << 21) | (\rs << 16) | (\u << 10) | (\sel << 4)
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	.endm
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#ifdef TOOLCHAIN_SUPPORTS_MSA
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	.macro	_cfcmsa	rd, cs
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	.set	push
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	.set	mips32r2
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	.set	fp=64
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	.set	msa
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	cfcmsa	\rd, $\cs
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	.set	pop
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	.endm
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	.macro	_ctcmsa	cd, rs
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	.set	push
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	.set	mips32r2
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	.set	fp=64
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	.set	msa
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	ctcmsa	$\cd, \rs
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	.set	pop
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	.endm
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	.macro	ld_b	wd, off, base
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	.set	push
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	.set	mips32r2
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	.set	fp=64
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	.set	msa
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	ld.b	$w\wd, \off(\base)
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	.set	pop
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	.endm
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	.macro	ld_h	wd, off, base
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	.set	push
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	.set	mips32r2
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	.set	fp=64
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	.set	msa
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	ld.h	$w\wd, \off(\base)
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	.set	pop
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	.endm
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	.macro	ld_w	wd, off, base
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	.set	push
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	.set	mips32r2
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	.set	fp=64
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	.set	msa
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	ld.w	$w\wd, \off(\base)
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	.set	pop
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	.endm
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	.macro	ld_d	wd, off, base
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	.set	push
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	.set	mips32r2
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	.set	fp=64
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	.set	msa
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	ld.d	$w\wd, \off(\base)
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	.set	pop
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	.endm
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	.macro	st_b	wd, off, base
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	.set	push
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	.set	mips32r2
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	.set	fp=64
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	.set	msa
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	st.b	$w\wd, \off(\base)
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	.set	pop
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	.endm
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	.macro	st_h	wd, off, base
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	.set	push
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	.set	mips32r2
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	.set	fp=64
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	.set	msa
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	st.h	$w\wd, \off(\base)
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	.set	pop
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	.endm
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	.macro	st_w	wd, off, base
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	.set	push
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	.set	mips32r2
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	.set	fp=64
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	.set	msa
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	st.w	$w\wd, \off(\base)
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	.set	pop
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	.endm
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	.macro	st_d	wd, off, base
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	.set	push
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	.set	mips32r2
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	.set	fp=64
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	.set	msa
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	st.d	$w\wd, \off(\base)
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	.set	pop
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	.endm
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	.macro	copy_s_w	ws, n
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	.set	push
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	.set	mips32r2
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	.set	fp=64
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	.set	msa
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	copy_s.w $1, $w\ws[\n]
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	.set	pop
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	.endm
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	.macro	copy_s_d	ws, n
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	.set	push
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	.set	mips64r2
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	.set	fp=64
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	.set	msa
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	copy_s.d $1, $w\ws[\n]
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	.set	pop
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	.endm
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	.macro	insert_w	wd, n
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	.set	push
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	.set	mips32r2
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	.set	fp=64
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	.set	msa
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	insert.w $w\wd[\n], $1
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	.set	pop
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	.endm
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	.macro	insert_d	wd, n
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	.set	push
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	.set	mips64r2
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	.set	fp=64
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	.set	msa
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	insert.d $w\wd[\n], $1
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	.set	pop
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	.endm
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#else
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	/*
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	 * Temporary until all toolchains in use include MSA support.
378
	 */
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	.macro	_cfcmsa	rd, cs
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	.set	push
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	.set	noat
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	.set	hardfloat
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	insn_if_mips 0x787e0059 | (\cs << 11)
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	insn32_if_mm 0x587e0056 | (\cs << 11)
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	move	\rd, $1
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	.set	pop
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	.endm
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	.macro	_ctcmsa	cd, rs
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	.set	push
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	.set	noat
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	.set	hardfloat
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	move	$1, \rs
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	insn_if_mips 0x783e0819 | (\cd << 6)
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	insn32_if_mm 0x583e0816 | (\cd << 6)
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	.set	pop
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	.endm
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	.macro	ld_b	wd, off, base
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	.set	push
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	.set	noat
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	.set	hardfloat
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	PTR_ADDU $1, \base, \off
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	insn_if_mips 0x78000820 | (\wd << 6)
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	insn32_if_mm 0x58000807 | (\wd << 6)
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	.set	pop
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	.endm
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409
	.macro	ld_h	wd, off, base
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	.set	push
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	.set	noat
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	.set	hardfloat
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	PTR_ADDU $1, \base, \off
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	insn_if_mips 0x78000821 | (\wd << 6)
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	insn32_if_mm 0x58000817 | (\wd << 6)
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	.set	pop
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	.endm
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	.macro	ld_w	wd, off, base
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	.set	push
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	.set	noat
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	.set	hardfloat
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	PTR_ADDU $1, \base, \off
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	insn_if_mips 0x78000822 | (\wd << 6)
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	insn32_if_mm 0x58000827 | (\wd << 6)
426
	.set	pop
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	.endm
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429
	.macro	ld_d	wd, off, base
430
	.set	push
431
	.set	noat
432
	.set	hardfloat
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	PTR_ADDU $1, \base, \off
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	insn_if_mips 0x78000823 | (\wd << 6)
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	insn32_if_mm 0x58000837 | (\wd << 6)
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	.set	pop
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	.endm
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439
	.macro	st_b	wd, off, base
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	.set	push
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	.set	noat
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	.set	hardfloat
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	PTR_ADDU $1, \base, \off
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	insn_if_mips 0x78000824 | (\wd << 6)
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	insn32_if_mm 0x5800080f | (\wd << 6)
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	.set	pop
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	.endm
448

449
	.macro	st_h	wd, off, base
450
	.set	push
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	.set	noat
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	.set	hardfloat
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	PTR_ADDU $1, \base, \off
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	insn_if_mips 0x78000825 | (\wd << 6)
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	insn32_if_mm 0x5800081f | (\wd << 6)
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	.set	pop
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	.endm
458

459
	.macro	st_w	wd, off, base
460
	.set	push
461
	.set	noat
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	.set	hardfloat
463
	PTR_ADDU $1, \base, \off
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	insn_if_mips 0x78000826 | (\wd << 6)
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	insn32_if_mm 0x5800082f | (\wd << 6)
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	.set	pop
467
	.endm
468

469
	.macro	st_d	wd, off, base
470
	.set	push
471
	.set	noat
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	.set	hardfloat
473
	PTR_ADDU $1, \base, \off
474
	insn_if_mips 0x78000827 | (\wd << 6)
475
	insn32_if_mm 0x5800083f | (\wd << 6)
476
	.set	pop
477
	.endm
478

479
	.macro	copy_s_w	ws, n
480
	.set	push
481
	.set	noat
482
	.set	hardfloat
483
	insn_if_mips 0x78b00059 | (\n << 16) | (\ws << 11)
484
	insn32_if_mm 0x58b00056 | (\n << 16) | (\ws << 11)
485
	.set	pop
486
	.endm
487

488
	.macro	copy_s_d	ws, n
489
	.set	push
490
	.set	noat
491
	.set	hardfloat
492
	insn_if_mips 0x78b80059 | (\n << 16) | (\ws << 11)
493
	insn32_if_mm 0x58b80056 | (\n << 16) | (\ws << 11)
494
	.set	pop
495
	.endm
496

497
	.macro	insert_w	wd, n
498
	.set	push
499
	.set	noat
500
	.set	hardfloat
501
	insn_if_mips 0x79300819 | (\n << 16) | (\wd << 6)
502
	insn32_if_mm 0x59300816 | (\n << 16) | (\wd << 6)
503
	.set	pop
504
	.endm
505

506
	.macro	insert_d	wd, n
507
	.set	push
508
	.set	noat
509
	.set	hardfloat
510
	insn_if_mips 0x79380819 | (\n << 16) | (\wd << 6)
511
	insn32_if_mm 0x59380816 | (\n << 16) | (\wd << 6)
512
	.set	pop
513
	.endm
514
#endif
515

516
#ifdef TOOLCHAIN_SUPPORTS_MSA
517
#define FPR_BASE_OFFS	THREAD_FPR0
518
#define FPR_BASE	$1
519
#else
520
#define FPR_BASE_OFFS	0
521
#define FPR_BASE	\thread
522
#endif
523

524
	.macro	msa_save_all	thread
525
	.set	push
526
	.set	noat
527
#ifdef TOOLCHAIN_SUPPORTS_MSA
528
	PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
529
#endif
530
	st_d	 0, THREAD_FPR0  - FPR_BASE_OFFS, FPR_BASE
531
	st_d	 1, THREAD_FPR1  - FPR_BASE_OFFS, FPR_BASE
532
	st_d	 2, THREAD_FPR2  - FPR_BASE_OFFS, FPR_BASE
533
	st_d	 3, THREAD_FPR3  - FPR_BASE_OFFS, FPR_BASE
534
	st_d	 4, THREAD_FPR4  - FPR_BASE_OFFS, FPR_BASE
535
	st_d	 5, THREAD_FPR5  - FPR_BASE_OFFS, FPR_BASE
536
	st_d	 6, THREAD_FPR6  - FPR_BASE_OFFS, FPR_BASE
537
	st_d	 7, THREAD_FPR7  - FPR_BASE_OFFS, FPR_BASE
538
	st_d	 8, THREAD_FPR8  - FPR_BASE_OFFS, FPR_BASE
539
	st_d	 9, THREAD_FPR9  - FPR_BASE_OFFS, FPR_BASE
540
	st_d	10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE
541
	st_d	11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE
542
	st_d	12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE
543
	st_d	13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE
544
	st_d	14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE
545
	st_d	15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE
546
	st_d	16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE
547
	st_d	17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE
548
	st_d	18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE
549
	st_d	19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE
550
	st_d	20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE
551
	st_d	21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE
552
	st_d	22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE
553
	st_d	23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE
554
	st_d	24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE
555
	st_d	25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE
556
	st_d	26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE
557
	st_d	27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE
558
	st_d	28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE
559
	st_d	29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE
560
	st_d	30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE
561
	st_d	31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE
562
	.set	hardfloat
563
	_cfcmsa	$1, MSA_CSR
564
	sw	$1, THREAD_MSA_CSR(\thread)
565
	.set	pop
566
	.endm
567

568
	.macro	msa_restore_all	thread
569
	.set	push
570
	.set	noat
571
	.set	hardfloat
572
	lw	$1, THREAD_MSA_CSR(\thread)
573
	_ctcmsa	MSA_CSR, $1
574
#ifdef TOOLCHAIN_SUPPORTS_MSA
575
	PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
576
#endif
577
	ld_d	 0, THREAD_FPR0  - FPR_BASE_OFFS, FPR_BASE
578
	ld_d	 1, THREAD_FPR1  - FPR_BASE_OFFS, FPR_BASE
579
	ld_d	 2, THREAD_FPR2  - FPR_BASE_OFFS, FPR_BASE
580
	ld_d	 3, THREAD_FPR3  - FPR_BASE_OFFS, FPR_BASE
581
	ld_d	 4, THREAD_FPR4  - FPR_BASE_OFFS, FPR_BASE
582
	ld_d	 5, THREAD_FPR5  - FPR_BASE_OFFS, FPR_BASE
583
	ld_d	 6, THREAD_FPR6  - FPR_BASE_OFFS, FPR_BASE
584
	ld_d	 7, THREAD_FPR7  - FPR_BASE_OFFS, FPR_BASE
585
	ld_d	 8, THREAD_FPR8  - FPR_BASE_OFFS, FPR_BASE
586
	ld_d	 9, THREAD_FPR9  - FPR_BASE_OFFS, FPR_BASE
587
	ld_d	10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE
588
	ld_d	11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE
589
	ld_d	12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE
590
	ld_d	13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE
591
	ld_d	14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE
592
	ld_d	15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE
593
	ld_d	16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE
594
	ld_d	17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE
595
	ld_d	18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE
596
	ld_d	19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE
597
	ld_d	20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE
598
	ld_d	21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE
599
	ld_d	22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE
600
	ld_d	23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE
601
	ld_d	24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE
602
	ld_d	25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE
603
	ld_d	26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE
604
	ld_d	27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE
605
	ld_d	28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE
606
	ld_d	29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE
607
	ld_d	30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE
608
	ld_d	31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE
609
	.set pop
610
	.endm
611

612
#undef FPR_BASE_OFFS
613
#undef FPR_BASE
614

615
	.macro	msa_init_upper wd
616
#ifdef CONFIG_64BIT
617
	insert_d \wd, 1
618
#else
619
	insert_w \wd, 2
620
	insert_w \wd, 3
621
#endif
622
	.endm
623

624
	.macro	msa_init_all_upper
625
	.set	push
626
	.set	noat
627
	.set	hardfloat
628
	not	$1, zero
629
	msa_init_upper	0
630
	msa_init_upper	1
631
	msa_init_upper	2
632
	msa_init_upper	3
633
	msa_init_upper	4
634
	msa_init_upper	5
635
	msa_init_upper	6
636
	msa_init_upper	7
637
	msa_init_upper	8
638
	msa_init_upper	9
639
	msa_init_upper	10
640
	msa_init_upper	11
641
	msa_init_upper	12
642
	msa_init_upper	13
643
	msa_init_upper	14
644
	msa_init_upper	15
645
	msa_init_upper	16
646
	msa_init_upper	17
647
	msa_init_upper	18
648
	msa_init_upper	19
649
	msa_init_upper	20
650
	msa_init_upper	21
651
	msa_init_upper	22
652
	msa_init_upper	23
653
	msa_init_upper	24
654
	msa_init_upper	25
655
	msa_init_upper	26
656
	msa_init_upper	27
657
	msa_init_upper	28
658
	msa_init_upper	29
659
	msa_init_upper	30
660
	msa_init_upper	31
661
	.set	pop
662
	.endm
663

664
#endif /* _ASM_ASMMACRO_H */
665

666
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