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torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/arch/mips/include/asm/cacheops.h
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/*

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 * Cache operations for the cache instruction.

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 *

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 * This file is subject to the terms and conditions of the GNU General Public

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 * License.  See the file "COPYING" in the main directory of this archive

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 * for more details.

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 *

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 * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle

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 * (C) Copyright 1999 Silicon Graphics, Inc.

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 */

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#ifndef __ASM_CACHEOPS_H

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#define __ASM_CACHEOPS_H

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/*

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 * Most cache ops are split into a 2 bit field identifying the cache, and a 3

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 * bit field identifying the cache operation.

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 */

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#define CacheOp_Cache			0x03

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#define CacheOp_Op			0x1c

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#define Cache_I				0x00

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#define Cache_D				0x01

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#define Cache_T				0x02

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#define Cache_V				0x02 /* Loongson-3 */

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#define Cache_S				0x03

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#define Index_Writeback_Inv		0x00

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#define Index_Load_Tag			0x04

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#define Index_Store_Tag			0x08

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#define Hit_Invalidate			0x10

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#define Hit_Writeback_Inv		0x14	/* not with Cache_I though */

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#define Hit_Writeback			0x18

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/*

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 * Cache Operations available on all MIPS processors with R4000-style caches

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 */

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#define Index_Invalidate_I		(Cache_I | Index_Writeback_Inv)

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#define Index_Writeback_Inv_D		(Cache_D | Index_Writeback_Inv)

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#define Index_Load_Tag_I		(Cache_I | Index_Load_Tag)

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#define Index_Load_Tag_D		(Cache_D | Index_Load_Tag)

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#define Index_Store_Tag_I		(Cache_I | Index_Store_Tag)

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#define Index_Store_Tag_D		(Cache_D | Index_Store_Tag)

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#define Hit_Invalidate_I		(Cache_I | Hit_Invalidate)

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#define Hit_Invalidate_D		(Cache_D | Hit_Invalidate)

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#define Hit_Writeback_Inv_D		(Cache_D | Hit_Writeback_Inv)

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/*

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 * R4000-specific cacheops

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 */

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#define Create_Dirty_Excl_D		(Cache_D | 0x0c)

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#define Fill_I				(Cache_I | 0x14)

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#define Hit_Writeback_I			(Cache_I | Hit_Writeback)

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#define Hit_Writeback_D			(Cache_D | Hit_Writeback)

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/*

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 * R4000SC and R4400SC-specific cacheops

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 */

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#define Cache_SI			0x02

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#define Cache_SD			0x03

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#define Index_Invalidate_SI		(Cache_SI | Index_Writeback_Inv)

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#define Index_Writeback_Inv_SD		(Cache_SD | Index_Writeback_Inv)

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#define Index_Load_Tag_SI		(Cache_SI | Index_Load_Tag)

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#define Index_Load_Tag_SD		(Cache_SD | Index_Load_Tag)

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#define Index_Store_Tag_SI		(Cache_SI | Index_Store_Tag)

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#define Index_Store_Tag_SD		(Cache_SD | Index_Store_Tag)

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#define Create_Dirty_Excl_SD		(Cache_SD | 0x0c)

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#define Hit_Invalidate_SI		(Cache_SI | Hit_Invalidate)

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#define Hit_Invalidate_SD		(Cache_SD | Hit_Invalidate)

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#define Hit_Writeback_Inv_SD		(Cache_SD | Hit_Writeback_Inv)

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#define Hit_Writeback_SD		(Cache_SD | Hit_Writeback)

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#define Hit_Set_Virtual_SI		(Cache_SI | 0x1c)

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#define Hit_Set_Virtual_SD		(Cache_SD | 0x1c)

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/*

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 * R5000-specific cacheops

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 */

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#define R5K_Page_Invalidate_S		(Cache_S | 0x14)

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/*

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 * RM7000-specific cacheops

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 */

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#define Page_Invalidate_T		(Cache_T | 0x14)

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#define Index_Store_Tag_T		(Cache_T | Index_Store_Tag)

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#define Index_Load_Tag_T		(Cache_T | Index_Load_Tag)

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/*

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 * R10000-specific cacheops

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 *

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 * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.

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 * Most of the _S cacheops are identical to the R4000SC _SD cacheops.

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 */

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#define Index_Writeback_Inv_S		(Cache_S | Index_Writeback_Inv)

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#define Index_Load_Tag_S		(Cache_S | Index_Load_Tag)

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#define Index_Store_Tag_S		(Cache_S | Index_Store_Tag)

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#define Hit_Invalidate_S		(Cache_S | Hit_Invalidate)

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#define Cache_Barrier			0x14

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#define Hit_Writeback_Inv_S		(Cache_S | Hit_Writeback_Inv)

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#define Index_Load_Data_I		(Cache_I | 0x18)

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#define Index_Load_Data_D		(Cache_D | 0x18)

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#define Index_Load_Data_S		(Cache_S | 0x18)

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#define Index_Store_Data_I		(Cache_I | 0x1c)

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#define Index_Store_Data_D		(Cache_D | 0x1c)

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#define Index_Store_Data_S		(Cache_S | 0x1c)

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/*

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 * Loongson2-specific cacheops

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 */

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#define Hit_Invalidate_I_Loongson2	(Cache_I | 0x00)

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/*

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 * Loongson3-specific cacheops

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 */

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#define Index_Writeback_Inv_V		(Cache_V | Index_Writeback_Inv)

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#endif	/* __ASM_CACHEOPS_H */

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