Path: blob/master/arch/mips/loongson2ef/fuloong-2e/irq.c
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// SPDX-License-Identifier: GPL-2.0-or-later1/*2* Copyright (C) 2007 Lemote Inc. & Institute of Computing Technology3* Author: Fuxin Zhang, [email protected]4*/5#include <linux/interrupt.h>67#include <asm/irq_cpu.h>8#include <asm/i8259.h>910#include <loongson.h>1112static void i8259_irqdispatch(void)13{14int irq;1516irq = i8259_irq();17if (irq >= 0)18do_IRQ(irq);19else20spurious_interrupt();21}2223asmlinkage void mach_irq_dispatch(unsigned int pending)24{25if (pending & CAUSEF_IP7)26do_IRQ(MIPS_CPU_IRQ_BASE + 7);27else if (pending & CAUSEF_IP6) /* perf counter loverflow */28return;29else if (pending & CAUSEF_IP5)30i8259_irqdispatch();31else if (pending & CAUSEF_IP2)32bonito_irqdispatch();33else34spurious_interrupt();35}3637void __init mach_init_irq(void)38{39int irq;4041/* init all controller42* 0-15 ------> i8259 interrupt43* 16-23 ------> mips cpu interrupt44* 32-63 ------> bonito irq45*/4647/* most bonito irq should be level triggered */48LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR |49LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES;5051/* Sets the first-level interrupt dispatcher. */52mips_cpu_irq_init();53init_i8259_irqs();54bonito_irq_init();5556/* bonito irq at IP2 */57irq = MIPS_CPU_IRQ_BASE + 2;58if (request_irq(irq, no_action, IRQF_NO_THREAD, "cascade", NULL))59pr_err("Failed to request irq %d (cascade)\n", irq);60/* 8259 irq at IP5 */61irq = MIPS_CPU_IRQ_BASE + 5;62if (request_irq(irq, no_action, IRQF_NO_THREAD, "cascade", NULL))63pr_err("Failed to request irq %d (cascade)\n", irq);64}656667