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torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/arch/mips/mm/c-r3k.c
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// SPDX-License-Identifier: GPL-2.0

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/*

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 * r2300.c: R2000 and R3000 specific mmu/cache code.

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 *

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 * Copyright (C) 1996 David S. Miller ([email protected])

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 *

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 * with a lot of changes to make this thing work for R3000s

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 * Tx39XX R4k style caches added. HK

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 * Copyright (C) 1998, 1999, 2000 Harald Koerfgen

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 * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov

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 * Copyright (C) 2001, 2004, 2007  Maciej W. Rozycki

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 */

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#include <linux/kernel.h>

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#include <linux/sched.h>

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#include <linux/smp.h>

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#include <linux/mm.h>

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#include <asm/page.h>

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#include <asm/mmu_context.h>

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#include <asm/isadep.h>

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#include <asm/io.h>

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#include <asm/bootinfo.h>

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#include <asm/cpu.h>

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static unsigned long icache_size, dcache_size;		/* Size in bytes */

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static unsigned long icache_lsize, dcache_lsize;	/* Size in bytes */

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unsigned long r3k_cache_size(unsigned long ca_flags)

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{

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	unsigned long flags, status, dummy, size;

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	volatile unsigned long *p;

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	p = (volatile unsigned long *) KSEG0;

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	flags = read_c0_status();

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	/* isolate cache space */

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	write_c0_status((ca_flags|flags)&~ST0_IEC);

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	*p = 0xa5a55a5a;

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	dummy = *p;

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	status = read_c0_status();

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	if (dummy != 0xa5a55a5a || (status & ST0_CM)) {

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		size = 0;

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	} else {

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		for (size = 128; size <= 0x40000; size <<= 1)

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			*(p + size) = 0;

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		*p = -1;

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		for (size = 128;

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		     (size <= 0x40000) && (*(p + size) == 0);

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		     size <<= 1)

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			;

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		if (size > 0x40000)

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			size = 0;

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	}

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	write_c0_status(flags);

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	return size * sizeof(*p);

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}

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unsigned long r3k_cache_lsize(unsigned long ca_flags)

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{

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	unsigned long flags, status, lsize, i;

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	volatile unsigned long *p;

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	p = (volatile unsigned long *) KSEG0;

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	flags = read_c0_status();

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	/* isolate cache space */

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	write_c0_status((ca_flags|flags)&~ST0_IEC);

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	for (i = 0; i < 128; i++)

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		*(p + i) = 0;

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	*(volatile unsigned char *)p = 0;

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	for (lsize = 1; lsize < 128; lsize <<= 1) {

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		*(p + lsize);

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		status = read_c0_status();

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		if (!(status & ST0_CM))

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			break;

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	}

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	for (i = 0; i < 128; i += lsize)

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		*(volatile unsigned char *)(p + i) = 0;

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	write_c0_status(flags);

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	return lsize * sizeof(*p);

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}

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static void r3k_probe_cache(void)

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{

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	dcache_size = r3k_cache_size(ST0_ISC);

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	if (dcache_size)

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		dcache_lsize = r3k_cache_lsize(ST0_ISC);

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	icache_size = r3k_cache_size(ST0_ISC|ST0_SWC);

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	if (icache_size)

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		icache_lsize = r3k_cache_lsize(ST0_ISC|ST0_SWC);

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}

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static void r3k_flush_icache_range(unsigned long start, unsigned long end)

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{

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	unsigned long size, i, flags;

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	volatile unsigned char *p;

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	size = end - start;

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	if (size > icache_size || KSEGX(start) != KSEG0) {

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		start = KSEG0;

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		size = icache_size;

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	}

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	p = (char *)start;

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	flags = read_c0_status();

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	/* isolate cache space */

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	write_c0_status((ST0_ISC|ST0_SWC|flags)&~ST0_IEC);

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	for (i = 0; i < size; i += 0x080) {

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		asm(	"sb\t$0, 0x000(%0)\n\t"

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			"sb\t$0, 0x004(%0)\n\t"

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			"sb\t$0, 0x008(%0)\n\t"

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			"sb\t$0, 0x00c(%0)\n\t"

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			"sb\t$0, 0x010(%0)\n\t"

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			"sb\t$0, 0x014(%0)\n\t"

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			"sb\t$0, 0x018(%0)\n\t"

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			"sb\t$0, 0x01c(%0)\n\t"

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			"sb\t$0, 0x020(%0)\n\t"

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			"sb\t$0, 0x024(%0)\n\t"

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			"sb\t$0, 0x028(%0)\n\t"

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			"sb\t$0, 0x02c(%0)\n\t"

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			"sb\t$0, 0x030(%0)\n\t"

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			"sb\t$0, 0x034(%0)\n\t"

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			"sb\t$0, 0x038(%0)\n\t"

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			"sb\t$0, 0x03c(%0)\n\t"

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			"sb\t$0, 0x040(%0)\n\t"

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			"sb\t$0, 0x044(%0)\n\t"

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			"sb\t$0, 0x048(%0)\n\t"

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			"sb\t$0, 0x04c(%0)\n\t"

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			"sb\t$0, 0x050(%0)\n\t"

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			"sb\t$0, 0x054(%0)\n\t"

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			"sb\t$0, 0x058(%0)\n\t"

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			"sb\t$0, 0x05c(%0)\n\t"

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			"sb\t$0, 0x060(%0)\n\t"

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			"sb\t$0, 0x064(%0)\n\t"

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			"sb\t$0, 0x068(%0)\n\t"

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			"sb\t$0, 0x06c(%0)\n\t"

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			"sb\t$0, 0x070(%0)\n\t"

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			"sb\t$0, 0x074(%0)\n\t"

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			"sb\t$0, 0x078(%0)\n\t"

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			"sb\t$0, 0x07c(%0)\n\t"

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			: : "r" (p) );

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		p += 0x080;

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	}

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	write_c0_status(flags);

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}

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static void r3k_flush_dcache_range(unsigned long start, unsigned long end)

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{

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	unsigned long size, i, flags;

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	volatile unsigned char *p;

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	size = end - start;

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	if (size > dcache_size || KSEGX(start) != KSEG0) {

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		start = KSEG0;

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		size = dcache_size;

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	}

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	p = (char *)start;

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	flags = read_c0_status();

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	/* isolate cache space */

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	write_c0_status((ST0_ISC|flags)&~ST0_IEC);

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	for (i = 0; i < size; i += 0x080) {

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		asm(	"sb\t$0, 0x000(%0)\n\t"

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			"sb\t$0, 0x004(%0)\n\t"

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			"sb\t$0, 0x008(%0)\n\t"

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			"sb\t$0, 0x00c(%0)\n\t"

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			"sb\t$0, 0x010(%0)\n\t"

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			"sb\t$0, 0x014(%0)\n\t"

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			"sb\t$0, 0x018(%0)\n\t"

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			"sb\t$0, 0x01c(%0)\n\t"

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			"sb\t$0, 0x020(%0)\n\t"

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			"sb\t$0, 0x024(%0)\n\t"

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			"sb\t$0, 0x028(%0)\n\t"

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			"sb\t$0, 0x02c(%0)\n\t"

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			"sb\t$0, 0x030(%0)\n\t"

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			"sb\t$0, 0x034(%0)\n\t"

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			"sb\t$0, 0x038(%0)\n\t"

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			"sb\t$0, 0x03c(%0)\n\t"

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			"sb\t$0, 0x040(%0)\n\t"

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			"sb\t$0, 0x044(%0)\n\t"

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			"sb\t$0, 0x048(%0)\n\t"

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			"sb\t$0, 0x04c(%0)\n\t"

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			"sb\t$0, 0x050(%0)\n\t"

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			"sb\t$0, 0x054(%0)\n\t"

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			"sb\t$0, 0x058(%0)\n\t"

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			"sb\t$0, 0x05c(%0)\n\t"

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			"sb\t$0, 0x060(%0)\n\t"

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			"sb\t$0, 0x064(%0)\n\t"

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			"sb\t$0, 0x068(%0)\n\t"

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			"sb\t$0, 0x06c(%0)\n\t"

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			"sb\t$0, 0x070(%0)\n\t"

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			"sb\t$0, 0x074(%0)\n\t"

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			"sb\t$0, 0x078(%0)\n\t"

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			"sb\t$0, 0x07c(%0)\n\t"

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			: : "r" (p) );

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		p += 0x080;

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	}

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	write_c0_status(flags);

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}

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static inline void r3k_flush_cache_all(void)

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{

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}

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static inline void r3k___flush_cache_all(void)

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{

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	r3k_flush_dcache_range(KSEG0, KSEG0 + dcache_size);

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	r3k_flush_icache_range(KSEG0, KSEG0 + icache_size);

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}

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static void r3k_flush_cache_mm(struct mm_struct *mm)

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{

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}

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static void r3k_flush_cache_range(struct vm_area_struct *vma,

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				  unsigned long start, unsigned long end)

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{

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}

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static void r3k_flush_cache_page(struct vm_area_struct *vma,

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				 unsigned long addr, unsigned long pfn)

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{

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	unsigned long kaddr = KSEG0ADDR(pfn << PAGE_SHIFT);

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	int exec = vma->vm_flags & VM_EXEC;

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	struct mm_struct *mm = vma->vm_mm;

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	pmd_t *pmdp;

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	pte_t *ptep;

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	pr_debug("cpage[%08llx,%08lx]\n",

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		 cpu_context(smp_processor_id(), mm), addr);

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	/* No ASID => no such page in the cache.  */

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	if (cpu_context(smp_processor_id(), mm) == 0)

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		return;

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	pmdp = pmd_off(mm, addr);

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	ptep = pte_offset_kernel(pmdp, addr);

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	/* Invalid => no such page in the cache.  */

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	if (!(pte_val(*ptep) & _PAGE_PRESENT))

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		return;

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	r3k_flush_dcache_range(kaddr, kaddr + PAGE_SIZE);

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	if (exec)

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		r3k_flush_icache_range(kaddr, kaddr + PAGE_SIZE);

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}

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static void r3k_flush_data_cache_page(unsigned long addr)

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{

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}

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static void r3k_flush_kernel_vmap_range(unsigned long vaddr, int size)

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{

270
	BUG();

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}

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static void r3k_dma_cache_wback_inv(unsigned long start, unsigned long size)

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{

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	/* Catch bad driver code */

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	BUG_ON(size == 0);

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278
	iob();

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	r3k_flush_dcache_range(start, start + size);

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}

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282
void r3k_cache_init(void)

283
{

284
	extern void build_clear_page(void);

285
	extern void build_copy_page(void);

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287
	r3k_probe_cache();

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289
	flush_cache_all = r3k_flush_cache_all;

290
	__flush_cache_all = r3k___flush_cache_all;

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	flush_cache_mm = r3k_flush_cache_mm;

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	flush_cache_range = r3k_flush_cache_range;

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	flush_cache_page = r3k_flush_cache_page;

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	flush_icache_range = r3k_flush_icache_range;

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	local_flush_icache_range = r3k_flush_icache_range;

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	__flush_icache_user_range = r3k_flush_icache_range;

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	__local_flush_icache_user_range = r3k_flush_icache_range;

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	__flush_kernel_vmap_range = r3k_flush_kernel_vmap_range;

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	flush_data_cache_page = r3k_flush_data_cache_page;

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	_dma_cache_wback_inv = r3k_dma_cache_wback_inv;

304
	_dma_cache_wback = r3k_dma_cache_wback_inv;

305
	_dma_cache_inv = r3k_dma_cache_wback_inv;

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	pr_info("Primary instruction cache %ldkB, linesize %ld bytes.\n",

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		icache_size >> 10, icache_lsize);

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	pr_info("Primary data cache %ldkB, linesize %ld bytes.\n",

310
		dcache_size >> 10, dcache_lsize);

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312
	build_clear_page();

313
	build_copy_page();

314
}

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