Book a Demo!
CoCalc Logo Icon
StoreFeaturesDocsShareSupportNewsAboutPoliciesSign UpSign In
torvalds
GitHub Repository: torvalds/linux
Path: blob/master/arch/mips/mm/init.c
26442 views
1
/*
2
* This file is subject to the terms and conditions of the GNU General Public
3
* License. See the file "COPYING" in the main directory of this archive
4
* for more details.
5
*
6
* Copyright (C) 1994 - 2000 Ralf Baechle
7
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8
* Kevin D. Kissell, [email protected] and Carsten Langgaard, [email protected]
9
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
10
*/
11
#include <linux/bug.h>
12
#include <linux/init.h>
13
#include <linux/export.h>
14
#include <linux/signal.h>
15
#include <linux/sched.h>
16
#include <linux/smp.h>
17
#include <linux/kernel.h>
18
#include <linux/errno.h>
19
#include <linux/string.h>
20
#include <linux/types.h>
21
#include <linux/pagemap.h>
22
#include <linux/ptrace.h>
23
#include <linux/mman.h>
24
#include <linux/mm.h>
25
#include <linux/memblock.h>
26
#include <linux/highmem.h>
27
#include <linux/swap.h>
28
#include <linux/proc_fs.h>
29
#include <linux/pfn.h>
30
#include <linux/hardirq.h>
31
#include <linux/gfp.h>
32
#include <linux/kcore.h>
33
#include <linux/initrd.h>
34
#include <linux/execmem.h>
35
36
#include <asm/bootinfo.h>
37
#include <asm/cachectl.h>
38
#include <asm/cpu.h>
39
#include <asm/dma.h>
40
#include <asm/maar.h>
41
#include <asm/mmu_context.h>
42
#include <asm/mmzone.h>
43
#include <asm/sections.h>
44
#include <asm/pgalloc.h>
45
#include <asm/tlb.h>
46
#include <asm/fixmap.h>
47
48
/*
49
* We have up to 8 empty zeroed pages so we can map one of the right colour
50
* when needed. This is necessary only on R4000 / R4400 SC and MC versions
51
* where we have to avoid VCED / VECI exceptions for good performance at
52
* any price. Since page is never written to after the initialization we
53
* don't have to care about aliases on other CPUs.
54
*/
55
unsigned long empty_zero_page, zero_page_mask;
56
EXPORT_SYMBOL_GPL(empty_zero_page);
57
EXPORT_SYMBOL(zero_page_mask);
58
59
/*
60
* Not static inline because used by IP27 special magic initialization code
61
*/
62
static void __init setup_zero_pages(void)
63
{
64
unsigned int order;
65
66
if (cpu_has_vce)
67
order = 3;
68
else
69
order = 0;
70
71
empty_zero_page = (unsigned long)memblock_alloc_or_panic(PAGE_SIZE << order, PAGE_SIZE);
72
73
zero_page_mask = ((PAGE_SIZE << order) - 1) & PAGE_MASK;
74
}
75
76
static void *__kmap_pgprot(struct page *page, unsigned long addr, pgprot_t prot)
77
{
78
enum fixed_addresses idx;
79
unsigned int old_mmid;
80
unsigned long vaddr, flags, entrylo;
81
unsigned long old_ctx;
82
pte_t pte;
83
int tlbidx;
84
85
BUG_ON(folio_test_dcache_dirty(page_folio(page)));
86
87
preempt_disable();
88
pagefault_disable();
89
idx = (addr >> PAGE_SHIFT) & (FIX_N_COLOURS - 1);
90
idx += in_interrupt() ? FIX_N_COLOURS : 0;
91
vaddr = __fix_to_virt(FIX_CMAP_END - idx);
92
pte = mk_pte(page, prot);
93
#if defined(CONFIG_XPA)
94
entrylo = pte_to_entrylo(pte.pte_high);
95
#elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
96
entrylo = pte.pte_high;
97
#else
98
entrylo = pte_to_entrylo(pte_val(pte));
99
#endif
100
101
local_irq_save(flags);
102
old_ctx = read_c0_entryhi();
103
write_c0_entryhi(vaddr & (PAGE_MASK << 1));
104
write_c0_entrylo0(entrylo);
105
write_c0_entrylo1(entrylo);
106
if (cpu_has_mmid) {
107
old_mmid = read_c0_memorymapid();
108
write_c0_memorymapid(MMID_KERNEL_WIRED);
109
}
110
#ifdef CONFIG_XPA
111
if (cpu_has_xpa) {
112
entrylo = (pte.pte_low & _PFNX_MASK);
113
writex_c0_entrylo0(entrylo);
114
writex_c0_entrylo1(entrylo);
115
}
116
#endif
117
tlbidx = num_wired_entries();
118
write_c0_wired(tlbidx + 1);
119
write_c0_index(tlbidx);
120
mtc0_tlbw_hazard();
121
tlb_write_indexed();
122
tlbw_use_hazard();
123
write_c0_entryhi(old_ctx);
124
if (cpu_has_mmid)
125
write_c0_memorymapid(old_mmid);
126
local_irq_restore(flags);
127
128
return (void*) vaddr;
129
}
130
131
void *kmap_coherent(struct page *page, unsigned long addr)
132
{
133
return __kmap_pgprot(page, addr, PAGE_KERNEL);
134
}
135
136
void *kmap_noncoherent(struct page *page, unsigned long addr)
137
{
138
return __kmap_pgprot(page, addr, PAGE_KERNEL_NC);
139
}
140
141
void kunmap_coherent(void)
142
{
143
unsigned int wired;
144
unsigned long flags, old_ctx;
145
146
local_irq_save(flags);
147
old_ctx = read_c0_entryhi();
148
wired = num_wired_entries() - 1;
149
write_c0_wired(wired);
150
write_c0_index(wired);
151
write_c0_entryhi(UNIQUE_ENTRYHI(wired));
152
write_c0_entrylo0(0);
153
write_c0_entrylo1(0);
154
mtc0_tlbw_hazard();
155
tlb_write_indexed();
156
tlbw_use_hazard();
157
write_c0_entryhi(old_ctx);
158
local_irq_restore(flags);
159
pagefault_enable();
160
preempt_enable();
161
}
162
163
void copy_user_highpage(struct page *to, struct page *from,
164
unsigned long vaddr, struct vm_area_struct *vma)
165
{
166
struct folio *src = page_folio(from);
167
void *vfrom, *vto;
168
169
vto = kmap_atomic(to);
170
if (cpu_has_dc_aliases &&
171
folio_mapped(src) && !folio_test_dcache_dirty(src)) {
172
vfrom = kmap_coherent(from, vaddr);
173
copy_page(vto, vfrom);
174
kunmap_coherent();
175
} else {
176
vfrom = kmap_atomic(from);
177
copy_page(vto, vfrom);
178
kunmap_atomic(vfrom);
179
}
180
if ((!cpu_has_ic_fills_f_dc) ||
181
pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
182
flush_data_cache_page((unsigned long)vto);
183
kunmap_atomic(vto);
184
/* Make sure this page is cleared on other CPU's too before using it */
185
smp_wmb();
186
}
187
188
void copy_to_user_page(struct vm_area_struct *vma,
189
struct page *page, unsigned long vaddr, void *dst, const void *src,
190
unsigned long len)
191
{
192
struct folio *folio = page_folio(page);
193
194
if (cpu_has_dc_aliases &&
195
folio_mapped(folio) && !folio_test_dcache_dirty(folio)) {
196
void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
197
memcpy(vto, src, len);
198
kunmap_coherent();
199
} else {
200
memcpy(dst, src, len);
201
if (cpu_has_dc_aliases)
202
folio_set_dcache_dirty(folio);
203
}
204
if (vma->vm_flags & VM_EXEC)
205
flush_cache_page(vma, vaddr, page_to_pfn(page));
206
}
207
208
void copy_from_user_page(struct vm_area_struct *vma,
209
struct page *page, unsigned long vaddr, void *dst, const void *src,
210
unsigned long len)
211
{
212
struct folio *folio = page_folio(page);
213
214
if (cpu_has_dc_aliases &&
215
folio_mapped(folio) && !folio_test_dcache_dirty(folio)) {
216
void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
217
memcpy(dst, vfrom, len);
218
kunmap_coherent();
219
} else {
220
memcpy(dst, src, len);
221
if (cpu_has_dc_aliases)
222
folio_set_dcache_dirty(folio);
223
}
224
}
225
EXPORT_SYMBOL_GPL(copy_from_user_page);
226
227
void __init fixrange_init(unsigned long start, unsigned long end,
228
pgd_t *pgd_base)
229
{
230
#ifdef CONFIG_HIGHMEM
231
pgd_t *pgd;
232
pud_t *pud;
233
pmd_t *pmd;
234
pte_t *pte;
235
int i, j, k;
236
unsigned long vaddr;
237
238
vaddr = start;
239
i = pgd_index(vaddr);
240
j = pud_index(vaddr);
241
k = pmd_index(vaddr);
242
pgd = pgd_base + i;
243
244
for ( ; (i < PTRS_PER_PGD) && (vaddr < end); pgd++, i++) {
245
pud = (pud_t *)pgd;
246
for ( ; (j < PTRS_PER_PUD) && (vaddr < end); pud++, j++) {
247
pmd = (pmd_t *)pud;
248
for (; (k < PTRS_PER_PMD) && (vaddr < end); pmd++, k++) {
249
if (pmd_none(*pmd)) {
250
pte = (pte_t *) memblock_alloc_low(PAGE_SIZE,
251
PAGE_SIZE);
252
if (!pte)
253
panic("%s: Failed to allocate %lu bytes align=%lx\n",
254
__func__, PAGE_SIZE,
255
PAGE_SIZE);
256
257
set_pmd(pmd, __pmd((unsigned long)pte));
258
BUG_ON(pte != pte_offset_kernel(pmd, 0));
259
}
260
vaddr += PMD_SIZE;
261
}
262
k = 0;
263
}
264
j = 0;
265
}
266
#endif
267
}
268
269
struct maar_walk_info {
270
struct maar_config cfg[16];
271
unsigned int num_cfg;
272
};
273
274
static int maar_res_walk(unsigned long start_pfn, unsigned long nr_pages,
275
void *data)
276
{
277
struct maar_walk_info *wi = data;
278
struct maar_config *cfg = &wi->cfg[wi->num_cfg];
279
unsigned int maar_align;
280
281
/* MAAR registers hold physical addresses right shifted by 4 bits */
282
maar_align = BIT(MIPS_MAAR_ADDR_SHIFT + 4);
283
284
/* Fill in the MAAR config entry */
285
cfg->lower = ALIGN(PFN_PHYS(start_pfn), maar_align);
286
cfg->upper = ALIGN_DOWN(PFN_PHYS(start_pfn + nr_pages), maar_align) - 1;
287
cfg->attrs = MIPS_MAAR_S;
288
289
/* Ensure we don't overflow the cfg array */
290
if (!WARN_ON(wi->num_cfg >= ARRAY_SIZE(wi->cfg)))
291
wi->num_cfg++;
292
293
return 0;
294
}
295
296
297
unsigned __weak platform_maar_init(unsigned num_pairs)
298
{
299
unsigned int num_configured;
300
struct maar_walk_info wi;
301
302
wi.num_cfg = 0;
303
walk_system_ram_range(0, max_pfn, &wi, maar_res_walk);
304
305
num_configured = maar_config(wi.cfg, wi.num_cfg, num_pairs);
306
if (num_configured < wi.num_cfg)
307
pr_warn("Not enough MAAR pairs (%u) for all memory regions (%u)\n",
308
num_pairs, wi.num_cfg);
309
310
return num_configured;
311
}
312
313
void maar_init(void)
314
{
315
unsigned num_maars, used, i;
316
phys_addr_t lower, upper, attr;
317
static struct {
318
struct maar_config cfgs[3];
319
unsigned used;
320
} recorded = { { { 0 } }, 0 };
321
322
if (!cpu_has_maar)
323
return;
324
325
/* Detect the number of MAARs */
326
write_c0_maari(~0);
327
back_to_back_c0_hazard();
328
num_maars = read_c0_maari() + 1;
329
330
/* MAARs should be in pairs */
331
WARN_ON(num_maars % 2);
332
333
/* Set MAARs using values we recorded already */
334
if (recorded.used) {
335
used = maar_config(recorded.cfgs, recorded.used, num_maars / 2);
336
BUG_ON(used != recorded.used);
337
} else {
338
/* Configure the required MAARs */
339
used = platform_maar_init(num_maars / 2);
340
}
341
342
/* Disable any further MAARs */
343
for (i = (used * 2); i < num_maars; i++) {
344
write_c0_maari(i);
345
back_to_back_c0_hazard();
346
write_c0_maar(0);
347
back_to_back_c0_hazard();
348
}
349
350
if (recorded.used)
351
return;
352
353
pr_info("MAAR configuration:\n");
354
for (i = 0; i < num_maars; i += 2) {
355
write_c0_maari(i);
356
back_to_back_c0_hazard();
357
upper = read_c0_maar();
358
#ifdef CONFIG_XPA
359
upper |= (phys_addr_t)readx_c0_maar() << MIPS_MAARX_ADDR_SHIFT;
360
#endif
361
362
write_c0_maari(i + 1);
363
back_to_back_c0_hazard();
364
lower = read_c0_maar();
365
#ifdef CONFIG_XPA
366
lower |= (phys_addr_t)readx_c0_maar() << MIPS_MAARX_ADDR_SHIFT;
367
#endif
368
369
attr = lower & upper;
370
lower = (lower & MIPS_MAAR_ADDR) << 4;
371
upper = ((upper & MIPS_MAAR_ADDR) << 4) | 0xffff;
372
373
pr_info(" [%d]: ", i / 2);
374
if ((attr & MIPS_MAAR_V) != MIPS_MAAR_V) {
375
pr_cont("disabled\n");
376
continue;
377
}
378
379
pr_cont("%pa-%pa", &lower, &upper);
380
381
if (attr & MIPS_MAAR_S)
382
pr_cont(" speculate");
383
384
pr_cont("\n");
385
386
/* Record the setup for use on secondary CPUs */
387
if (used <= ARRAY_SIZE(recorded.cfgs)) {
388
recorded.cfgs[recorded.used].lower = lower;
389
recorded.cfgs[recorded.used].upper = upper;
390
recorded.cfgs[recorded.used].attrs = attr;
391
recorded.used++;
392
}
393
}
394
}
395
396
#ifndef CONFIG_NUMA
397
void __init paging_init(void)
398
{
399
unsigned long max_zone_pfns[MAX_NR_ZONES];
400
401
pagetable_init();
402
403
#ifdef CONFIG_ZONE_DMA
404
max_zone_pfns[ZONE_DMA] = MAX_DMA_PFN;
405
#endif
406
#ifdef CONFIG_ZONE_DMA32
407
max_zone_pfns[ZONE_DMA32] = MAX_DMA32_PFN;
408
#endif
409
max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
410
#ifdef CONFIG_HIGHMEM
411
max_zone_pfns[ZONE_HIGHMEM] = highend_pfn;
412
413
if (cpu_has_dc_aliases && max_low_pfn != highend_pfn) {
414
printk(KERN_WARNING "This processor doesn't support highmem."
415
" %ldk highmem ignored\n",
416
(highend_pfn - max_low_pfn) << (PAGE_SHIFT - 10));
417
max_zone_pfns[ZONE_HIGHMEM] = max_low_pfn;
418
}
419
#endif
420
421
free_area_init(max_zone_pfns);
422
}
423
424
#ifdef CONFIG_64BIT
425
static struct kcore_list kcore_kseg0;
426
#endif
427
428
void __init arch_mm_preinit(void)
429
{
430
/*
431
* When PFN_PTE_SHIFT is greater than PAGE_SHIFT we won't have enough PTE
432
* bits to hold a full 32b physical address on MIPS32 systems.
433
*/
434
BUILD_BUG_ON(IS_ENABLED(CONFIG_32BIT) && (PFN_PTE_SHIFT > PAGE_SHIFT));
435
436
maar_init();
437
setup_zero_pages(); /* Setup zeroed pages. */
438
439
#ifdef CONFIG_64BIT
440
if ((unsigned long) &_text > (unsigned long) CKSEG0)
441
/* The -4 is a hack so that user tools don't have to handle
442
the overflow. */
443
kclist_add(&kcore_kseg0, (void *) CKSEG0,
444
0x80000000 - 4, KCORE_TEXT);
445
#endif
446
}
447
#else /* CONFIG_NUMA */
448
void __init arch_mm_preinit(void)
449
{
450
setup_zero_pages(); /* This comes from node 0 */
451
}
452
#endif /* !CONFIG_NUMA */
453
454
void free_init_pages(const char *what, unsigned long begin, unsigned long end)
455
{
456
unsigned long pfn;
457
458
for (pfn = PFN_UP(begin); pfn < PFN_DOWN(end); pfn++) {
459
struct page *page = pfn_to_page(pfn);
460
void *addr = phys_to_virt(PFN_PHYS(pfn));
461
462
memset(addr, POISON_FREE_INITMEM, PAGE_SIZE);
463
free_reserved_page(page);
464
}
465
printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10);
466
}
467
468
void (*free_init_pages_eva)(void *begin, void *end) = NULL;
469
470
void __weak __init prom_free_prom_memory(void)
471
{
472
/* nothing to do */
473
}
474
475
void __ref free_initmem(void)
476
{
477
prom_free_prom_memory();
478
/*
479
* Let the platform define a specific function to free the
480
* init section since EVA may have used any possible mapping
481
* between virtual and physical addresses.
482
*/
483
if (free_init_pages_eva)
484
free_init_pages_eva((void *)&__init_begin, (void *)&__init_end);
485
else
486
free_initmem_default(POISON_FREE_INITMEM);
487
}
488
489
#ifdef CONFIG_HAVE_SETUP_PER_CPU_AREA
490
unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
491
EXPORT_SYMBOL(__per_cpu_offset);
492
493
static int __init pcpu_cpu_distance(unsigned int from, unsigned int to)
494
{
495
return node_distance(cpu_to_node(from), cpu_to_node(to));
496
}
497
498
static int __init pcpu_cpu_to_node(int cpu)
499
{
500
return cpu_to_node(cpu);
501
}
502
503
void __init setup_per_cpu_areas(void)
504
{
505
unsigned long delta;
506
unsigned int cpu;
507
int rc;
508
509
/*
510
* Always reserve area for module percpu variables. That's
511
* what the legacy allocator did.
512
*/
513
rc = pcpu_embed_first_chunk(PERCPU_MODULE_RESERVE,
514
PERCPU_DYNAMIC_RESERVE, PAGE_SIZE,
515
pcpu_cpu_distance,
516
pcpu_cpu_to_node);
517
if (rc < 0)
518
panic("Failed to initialize percpu areas.");
519
520
delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
521
for_each_possible_cpu(cpu)
522
__per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
523
}
524
#endif
525
526
#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
527
unsigned long pgd_current[NR_CPUS];
528
#endif
529
530
/*
531
* Align swapper_pg_dir in to 64K, allows its address to be loaded
532
* with a single LUI instruction in the TLB handlers. If we used
533
* __aligned(64K), its size would get rounded up to the alignment
534
* size, and waste space. So we place it in its own section and align
535
* it in the linker script.
536
*/
537
pgd_t swapper_pg_dir[PTRS_PER_PGD] __section(".bss..swapper_pg_dir");
538
#ifndef __PAGETABLE_PUD_FOLDED
539
pud_t invalid_pud_table[PTRS_PER_PUD] __page_aligned_bss;
540
#endif
541
#ifndef __PAGETABLE_PMD_FOLDED
542
pmd_t invalid_pmd_table[PTRS_PER_PMD] __page_aligned_bss;
543
EXPORT_SYMBOL_GPL(invalid_pmd_table);
544
#endif
545
pte_t invalid_pte_table[PTRS_PER_PTE] __page_aligned_bss;
546
EXPORT_SYMBOL(invalid_pte_table);
547
548
#ifdef CONFIG_EXECMEM
549
#ifdef MODULES_VADDR
550
static struct execmem_info execmem_info __ro_after_init;
551
552
struct execmem_info __init *execmem_arch_setup(void)
553
{
554
execmem_info = (struct execmem_info){
555
.ranges = {
556
[EXECMEM_DEFAULT] = {
557
.start = MODULES_VADDR,
558
.end = MODULES_END,
559
.pgprot = PAGE_KERNEL,
560
.alignment = 1,
561
},
562
},
563
};
564
565
return &execmem_info;
566
}
567
#endif
568
#endif /* CONFIG_EXECMEM */
569
570