CoCalc -- uasm-mips.c

GitHub Repository: torvalds/linux
Path: blob/master/arch/mips/mm/uasm-mips.c
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/*
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 * This file is subject to the terms and conditions of the GNU General Public
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 * License.  See the file "COPYING" in the main directory of this archive
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 * for more details.
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 *
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 * A small micro-assembler. It is intentionally kept simple, does only
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 * support a subset of instructions, and does not try to hide pipeline
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 * effects like branch delay slots.
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 *
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 * Copyright (C) 2004, 2005, 2006, 2008	 Thiemo Seufer
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 * Copyright (C) 2005, 2007  Maciej W. Rozycki
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 * Copyright (C) 2006  Ralf Baechle ([email protected])
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 * Copyright (C) 2012, 2013  MIPS Technologies, Inc.  All rights reserved.
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 */
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#include <linux/kernel.h>
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#include <linux/types.h>
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19
#include <asm/inst.h>
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#include <asm/elf.h>
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#include <asm/bugs.h>
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#include <asm/uasm.h>
23

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#define RS_MASK		0x1f
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#define RS_SH		21
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#define RT_MASK		0x1f
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#define RT_SH		16
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#define SCIMM_MASK	0xfffff
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#define SCIMM_SH	6
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/* This macro sets the non-variable bits of an instruction. */
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#define M(a, b, c, d, e, f)					\
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	((a) << OP_SH						\
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	 | (b) << RS_SH						\
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	 | (c) << RT_SH						\
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	 | (d) << RD_SH						\
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	 | (e) << RE_SH						\
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	 | (f) << FUNC_SH)
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/* This macro sets the non-variable bits of an R6 instruction. */
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#define M6(a, b, c, d, e)					\
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	((a) << OP_SH						\
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	 | (b) << RS_SH						\
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	 | (c) << RT_SH						\
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	 | (d) << SIMM9_SH					\
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	 | (e) << FUNC_SH)
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#include "uasm.c"
49

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static const struct insn insn_table[insn_invalid] = {
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	[insn_addiu]	= {M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
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	[insn_addu]	= {M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD},
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	[insn_and]	= {M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD},
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	[insn_andi]	= {M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM},
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	[insn_bbit0]	= {M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
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	[insn_bbit1]	= {M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
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	[insn_beq]	= {M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
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	[insn_beql]	= {M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
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	[insn_bgez]	= {M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM},
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	[insn_bgezl]	= {M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM},
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	[insn_bgtz]	= {M(bgtz_op, 0, 0, 0, 0, 0), RS | BIMM},
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	[insn_blez]	= {M(blez_op, 0, 0, 0, 0, 0), RS | BIMM},
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	[insn_bltz]	= {M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM},
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	[insn_bltzl]	= {M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM},
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	[insn_bne]	= {M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
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	[insn_break]	= {M(spec_op, 0, 0, 0, 0, break_op), SCIMM},
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#ifndef CONFIG_CPU_MIPSR6
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	[insn_cache]	= {M(cache_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
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#else
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	[insn_cache]	= {M6(spec3_op, 0, 0, 0, cache6_op),  RS | RT | SIMM9},
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#endif
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	[insn_cfc1]	= {M(cop1_op, cfc_op, 0, 0, 0, 0), RT | RD},
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	[insn_cfcmsa]	= {M(msa_op, 0, msa_cfc_op, 0, 0, msa_elm_op), RD | RE},
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	[insn_ctc1]	= {M(cop1_op, ctc_op, 0, 0, 0, 0), RT | RD},
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	[insn_ctcmsa]	= {M(msa_op, 0, msa_ctc_op, 0, 0, msa_elm_op), RD | RE},
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	[insn_daddiu]	= {M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
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	[insn_daddu]	= {M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD},
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	[insn_ddivu]	= {M(spec_op, 0, 0, 0, 0, ddivu_op), RS | RT},
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	[insn_ddivu_r6]	= {M(spec_op, 0, 0, 0, ddivu_ddivu6_op, ddivu_op),
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				RS | RT | RD},
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	[insn_di]	= {M(cop0_op, mfmc0_op, 0, 12, 0, 0), RT},
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	[insn_dins]	= {M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE},
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	[insn_dinsm]	= {M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE},
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	[insn_dinsu]	= {M(spec3_op, 0, 0, 0, 0, dinsu_op), RS | RT | RD | RE},
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	[insn_divu]	= {M(spec_op, 0, 0, 0, 0, divu_op), RS | RT},
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	[insn_divu_r6]	= {M(spec_op, 0, 0, 0, divu_divu6_op, divu_op),
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				RS | RT | RD},
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	[insn_dmfc0]	= {M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
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	[insn_dmodu]	= {M(spec_op, 0, 0, 0, ddivu_dmodu_op, ddivu_op),
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				RS | RT | RD},
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	[insn_dmtc0]	= {M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
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	[insn_dmultu]	= {M(spec_op, 0, 0, 0, 0, dmultu_op), RS | RT},
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	[insn_dmulu]	= {M(spec_op, 0, 0, 0, dmultu_dmulu_op, dmultu_op),
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				RS | RT | RD},
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	[insn_drotr]	= {M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE},
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	[insn_drotr32]	= {M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE},
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	[insn_dsbh]	= {M(spec3_op, 0, 0, 0, dsbh_op, dbshfl_op), RT | RD},
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	[insn_dshd]	= {M(spec3_op, 0, 0, 0, dshd_op, dbshfl_op), RT | RD},
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	[insn_dsll]	= {M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE},
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	[insn_dsll32]	= {M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE},
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	[insn_dsllv]	= {M(spec_op, 0, 0, 0, 0, dsllv_op),  RS | RT | RD},
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	[insn_dsra]	= {M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE},
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	[insn_dsra32]	= {M(spec_op, 0, 0, 0, 0, dsra32_op), RT | RD | RE},
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	[insn_dsrav]	= {M(spec_op, 0, 0, 0, 0, dsrav_op),  RS | RT | RD},
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	[insn_dsrl]	= {M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE},
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	[insn_dsrl32]	= {M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE},
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	[insn_dsrlv]	= {M(spec_op, 0, 0, 0, 0, dsrlv_op),  RS | RT | RD},
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	[insn_dsubu]	= {M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD},
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	[insn_eret]	= {M(cop0_op, cop_op, 0, 0, 0, eret_op),  0},
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	[insn_ext]	= {M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE},
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	[insn_ins]	= {M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE},
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	[insn_j]	= {M(j_op, 0, 0, 0, 0, 0),  JIMM},
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	[insn_jal]	= {M(jal_op, 0, 0, 0, 0, 0),	JIMM},
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	[insn_jalr]	= {M(spec_op, 0, 0, 0, 0, jalr_op), RS | RD},
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#ifndef CONFIG_CPU_MIPSR6
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	[insn_jr]	= {M(spec_op, 0, 0, 0, 0, jr_op),  RS},
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#else
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	[insn_jr]	= {M(spec_op, 0, 0, 0, 0, jalr_op),  RS},
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#endif
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	[insn_lb]	= {M(lb_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
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	[insn_lbu]	= {M(lbu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
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	[insn_ld]	= {M(ld_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
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	[insn_lddir]	= {M(lwc2_op, 0, 0, 0, lddir_op, mult_op), RS | RT | RD},
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	[insn_ldpte]	= {M(lwc2_op, 0, 0, 0, ldpte_op, mult_op), RS | RD},
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	[insn_ldx]	= {M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD},
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	[insn_lh]	= {M(lh_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
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	[insn_lhu]	= {M(lhu_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
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#ifndef CONFIG_CPU_MIPSR6
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	[insn_ll]	= {M(ll_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
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	[insn_lld]	= {M(lld_op, 0, 0, 0, 0, 0),	RS | RT | SIMM},
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#else
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	[insn_ll]	= {M6(spec3_op, 0, 0, 0, ll6_op),  RS | RT | SIMM9},
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	[insn_lld]	= {M6(spec3_op, 0, 0, 0, lld6_op),  RS | RT | SIMM9},
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#endif
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	[insn_lui]	= {M(lui_op, 0, 0, 0, 0, 0),	RT | SIMM},
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	[insn_lw]	= {M(lw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
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	[insn_lwu]	= {M(lwu_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
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	[insn_lwx]	= {M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD},
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	[insn_mfc0]	= {M(cop0_op, mfc_op, 0, 0, 0, 0),  RT | RD | SET},
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	[insn_mfhc0]	= {M(cop0_op, mfhc0_op, 0, 0, 0, 0),  RT | RD | SET},
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	[insn_mfhi]	= {M(spec_op, 0, 0, 0, 0, mfhi_op), RD},
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	[insn_mflo]	= {M(spec_op, 0, 0, 0, 0, mflo_op), RD},
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	[insn_modu]	= {M(spec_op, 0, 0, 0, divu_modu_op, divu_op),
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				RS | RT | RD},
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	[insn_movn]	= {M(spec_op, 0, 0, 0, 0, movn_op), RS | RT | RD},
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	[insn_movz]	= {M(spec_op, 0, 0, 0, 0, movz_op), RS | RT | RD},
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	[insn_mtc0]	= {M(cop0_op, mtc_op, 0, 0, 0, 0),  RT | RD | SET},
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	[insn_mthc0]	= {M(cop0_op, mthc0_op, 0, 0, 0, 0),  RT | RD | SET},
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	[insn_mthi]	= {M(spec_op, 0, 0, 0, 0, mthi_op), RS},
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	[insn_mtlo]	= {M(spec_op, 0, 0, 0, 0, mtlo_op), RS},
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	[insn_mulu]	= {M(spec_op, 0, 0, 0, multu_mulu_op, multu_op),
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				RS | RT | RD},
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	[insn_muhu]	= {M(spec_op, 0, 0, 0, multu_muhu_op, multu_op),
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				RS | RT | RD},
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#ifndef CONFIG_CPU_MIPSR6
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	[insn_mul]	= {M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD},
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#else
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	[insn_mul]	= {M(spec_op, 0, 0, 0, mult_mul_op, mult_op), RS | RT | RD},
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#endif
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	[insn_multu]	= {M(spec_op, 0, 0, 0, 0, multu_op), RS | RT},
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	[insn_nor]	= {M(spec_op, 0, 0, 0, 0, nor_op),  RS | RT | RD},
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	[insn_or]	= {M(spec_op, 0, 0, 0, 0, or_op),  RS | RT | RD},
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	[insn_ori]	= {M(ori_op, 0, 0, 0, 0, 0),	RS | RT | UIMM},
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#ifndef CONFIG_CPU_MIPSR6
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	[insn_pref]	= {M(pref_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
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#else
167
	[insn_pref]	= {M6(spec3_op, 0, 0, 0, pref6_op),  RS | RT | SIMM9},
168
#endif
169
	[insn_rfe]	= {M(cop0_op, cop_op, 0, 0, 0, rfe_op),  0},
170
	[insn_rotr]	= {M(spec_op, 1, 0, 0, 0, srl_op),  RT | RD | RE},
171
	[insn_sb]	= {M(sb_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
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#ifndef CONFIG_CPU_MIPSR6
173
	[insn_sc]	= {M(sc_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
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	[insn_scd]	= {M(scd_op, 0, 0, 0, 0, 0),	RS | RT | SIMM},
175
#else
176
	[insn_sc]	= {M6(spec3_op, 0, 0, 0, sc6_op),  RS | RT | SIMM9},
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	[insn_scd]	= {M6(spec3_op, 0, 0, 0, scd6_op),  RS | RT | SIMM9},
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#endif
179
	[insn_sd]	= {M(sd_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
180
	[insn_seleqz]	= {M(spec_op, 0, 0, 0, 0, seleqz_op), RS | RT | RD},
181
	[insn_selnez]	= {M(spec_op, 0, 0, 0, 0, selnez_op), RS | RT | RD},
182
	[insn_sh]	= {M(sh_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
183
	[insn_sll]	= {M(spec_op, 0, 0, 0, 0, sll_op),  RT | RD | RE},
184
	[insn_sllv]	= {M(spec_op, 0, 0, 0, 0, sllv_op),  RS | RT | RD},
185
	[insn_slt]	= {M(spec_op, 0, 0, 0, 0, slt_op),  RS | RT | RD},
186
	[insn_slti]	= {M(slti_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
187
	[insn_sltiu]	= {M(sltiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
188
	[insn_sltu]	= {M(spec_op, 0, 0, 0, 0, sltu_op), RS | RT | RD},
189
	[insn_sra]	= {M(spec_op, 0, 0, 0, 0, sra_op),  RT | RD | RE},
190
	[insn_srav]	= {M(spec_op, 0, 0, 0, 0, srav_op), RS | RT | RD},
191
	[insn_srl]	= {M(spec_op, 0, 0, 0, 0, srl_op),  RT | RD | RE},
192
	[insn_srlv]	= {M(spec_op, 0, 0, 0, 0, srlv_op),  RS | RT | RD},
193
	[insn_subu]	= {M(spec_op, 0, 0, 0, 0, subu_op),	RS | RT | RD},
194
	[insn_sw]	= {M(sw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM},
195
	[insn_sync]	= {M(spec_op, 0, 0, 0, 0, sync_op), RE},
196
	[insn_syscall]	= {M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
197
	[insn_tlbp]	= {M(cop0_op, cop_op, 0, 0, 0, tlbp_op),  0},
198
	[insn_tlbr]	= {M(cop0_op, cop_op, 0, 0, 0, tlbr_op),  0},
199
	[insn_tlbwi]	= {M(cop0_op, cop_op, 0, 0, 0, tlbwi_op),  0},
200
	[insn_tlbwr]	= {M(cop0_op, cop_op, 0, 0, 0, tlbwr_op),  0},
201
	[insn_wait]	= {M(cop0_op, cop_op, 0, 0, 0, wait_op), SCIMM},
202
	[insn_wsbh]	= {M(spec3_op, 0, 0, 0, wsbh_op, bshfl_op), RT | RD},
203
	[insn_xor]	= {M(spec_op, 0, 0, 0, 0, xor_op),  RS | RT | RD},
204
	[insn_xori]	= {M(xori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM},
205
	[insn_yield]	= {M(spec3_op, 0, 0, 0, 0, yield_op), RS | RD},
206
};
207

208
#undef M
209

210
static inline u32 build_bimm(s32 arg)
211
{
212
	WARN(arg > 0x1ffff || arg < -0x20000,
213
	     KERN_WARNING "Micro-assembler field overflow\n");
214

215
	WARN(arg & 0x3, KERN_WARNING "Invalid micro-assembler branch target\n");
216

217
	return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
218
}
219

220
static inline u32 build_jimm(u32 arg)
221
{
222
	WARN(arg & ~(JIMM_MASK << 2),
223
	     KERN_WARNING "Micro-assembler field overflow\n");
224

225
	return (arg >> 2) & JIMM_MASK;
226
}
227

228
/*
229
 * The order of opcode arguments is implicitly left to right,
230
 * starting with RS and ending with FUNC or IMM.
231
 */
232
static void build_insn(u32 **buf, enum opcode opc, ...)
233
{
234
	const struct insn *ip;
235
	va_list ap;
236
	u32 op;
237

238
	if (opc < 0 || opc >= insn_invalid ||
239
	    (opc == insn_daddiu && r4k_daddiu_bug()) ||
240
	    (insn_table[opc].match == 0 && insn_table[opc].fields == 0))
241
		panic("Unsupported Micro-assembler instruction %d", opc);
242

243
	ip = &insn_table[opc];
244

245
	op = ip->match;
246
	va_start(ap, opc);
247
	if (ip->fields & RS)
248
		op |= build_rs(va_arg(ap, u32));
249
	if (ip->fields & RT)
250
		op |= build_rt(va_arg(ap, u32));
251
	if (ip->fields & RD)
252
		op |= build_rd(va_arg(ap, u32));
253
	if (ip->fields & RE)
254
		op |= build_re(va_arg(ap, u32));
255
	if (ip->fields & SIMM)
256
		op |= build_simm(va_arg(ap, s32));
257
	if (ip->fields & UIMM)
258
		op |= build_uimm(va_arg(ap, u32));
259
	if (ip->fields & BIMM)
260
		op |= build_bimm(va_arg(ap, s32));
261
	if (ip->fields & JIMM)
262
		op |= build_jimm(va_arg(ap, u32));
263
	if (ip->fields & FUNC)
264
		op |= build_func(va_arg(ap, u32));
265
	if (ip->fields & SET)
266
		op |= build_set(va_arg(ap, u32));
267
	if (ip->fields & SCIMM)
268
		op |= build_scimm(va_arg(ap, u32));
269
	if (ip->fields & SIMM9)
270
		op |= build_scimm9(va_arg(ap, u32));
271
	va_end(ap);
272

273
	**buf = op;
274
	(*buf)++;
275
}
276

277
static inline void
278
__resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
279
{
280
	long laddr = (long)lab->addr;
281
	long raddr = (long)rel->addr;
282

283
	switch (rel->type) {
284
	case R_MIPS_PC16:
285
		*rel->addr |= build_bimm(laddr - (raddr + 4));
286
		break;
287

288
	default:
289
		panic("Unsupported Micro-assembler relocation %d",
290
		      rel->type);
291
	}
292
}
293

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