CoCalc -- early

GitHub Repository: torvalds/linux
Path: blob/master/arch/mips/pic32/pic32mzda/early_pin.c
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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 * Joshua Henderson <[email protected]>
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 * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.
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 */
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#include <asm/io.h>
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#include "early_pin.h"
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#define PPS_BASE 0x1f800000
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/* Input PPS Registers */
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#define INT1R 0x1404
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#define INT2R 0x1408
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#define INT3R 0x140C
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#define INT4R 0x1410
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#define T2CKR 0x1418
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#define T3CKR 0x141C
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#define T4CKR 0x1420
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#define T5CKR 0x1424
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#define T6CKR 0x1428
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#define T7CKR 0x142C
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#define T8CKR 0x1430
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#define T9CKR 0x1434
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#define IC1R 0x1438
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#define IC2R 0x143C
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#define IC3R 0x1440
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#define IC4R 0x1444
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#define IC5R 0x1448
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#define IC6R 0x144C
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#define IC7R 0x1450
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#define IC8R 0x1454
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#define IC9R 0x1458
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#define OCFAR 0x1460
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#define U1RXR 0x1468
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#define U1CTSR 0x146C
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#define U2RXR 0x1470
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#define U2CTSR 0x1474
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#define U3RXR 0x1478
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#define U3CTSR 0x147C
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#define U4RXR 0x1480
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#define U4CTSR 0x1484
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#define U5RXR 0x1488
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#define U5CTSR 0x148C
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#define U6RXR 0x1490
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#define U6CTSR 0x1494
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#define SDI1R 0x149C
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#define SS1R 0x14A0
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#define SDI2R 0x14A8
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#define SS2R 0x14AC
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#define SDI3R 0x14B4
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#define SS3R 0x14B8
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#define SDI4R 0x14C0
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#define SS4R 0x14C4
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#define SDI5R 0x14CC
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#define SS5R 0x14D0
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#define SDI6R 0x14D8
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#define SS6R 0x14DC
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#define C1RXR 0x14E0
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#define C2RXR 0x14E4
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#define REFCLKI1R 0x14E8
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#define REFCLKI3R 0x14F0
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#define REFCLKI4R 0x14F4
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static const struct
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{
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	int function;
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	int reg;
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} input_pin_reg[] = {
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	{ IN_FUNC_INT3, INT3R },
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	{ IN_FUNC_T2CK, T2CKR },
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	{ IN_FUNC_T6CK, T6CKR },
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	{ IN_FUNC_IC3, IC3R  },
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	{ IN_FUNC_IC7, IC7R },
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	{ IN_FUNC_U1RX, U1RXR },
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	{ IN_FUNC_U2CTS, U2CTSR },
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	{ IN_FUNC_U5RX, U5RXR },
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	{ IN_FUNC_U6CTS, U6CTSR },
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	{ IN_FUNC_SDI1, SDI1R },
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	{ IN_FUNC_SDI3, SDI3R },
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	{ IN_FUNC_SDI5, SDI5R },
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	{ IN_FUNC_SS6, SS6R },
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	{ IN_FUNC_REFCLKI1, REFCLKI1R },
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	{ IN_FUNC_INT4, INT4R },
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	{ IN_FUNC_T5CK, T5CKR },
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	{ IN_FUNC_T7CK, T7CKR },
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	{ IN_FUNC_IC4, IC4R },
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	{ IN_FUNC_IC8, IC8R },
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	{ IN_FUNC_U3RX, U3RXR },
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	{ IN_FUNC_U4CTS, U4CTSR },
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	{ IN_FUNC_SDI2, SDI2R },
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	{ IN_FUNC_SDI4, SDI4R },
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	{ IN_FUNC_C1RX, C1RXR },
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	{ IN_FUNC_REFCLKI4, REFCLKI4R },
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	{ IN_FUNC_INT2, INT2R },
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	{ IN_FUNC_T3CK, T3CKR },
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	{ IN_FUNC_T8CK, T8CKR },
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	{ IN_FUNC_IC2, IC2R },
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	{ IN_FUNC_IC5, IC5R },
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	{ IN_FUNC_IC9, IC9R },
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	{ IN_FUNC_U1CTS, U1CTSR },
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	{ IN_FUNC_U2RX, U2RXR },
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	{ IN_FUNC_U5CTS, U5CTSR },
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	{ IN_FUNC_SS1, SS1R },
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	{ IN_FUNC_SS3, SS3R },
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	{ IN_FUNC_SS4, SS4R },
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	{ IN_FUNC_SS5, SS5R },
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	{ IN_FUNC_C2RX, C2RXR },
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	{ IN_FUNC_INT1, INT1R },
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	{ IN_FUNC_T4CK, T4CKR },
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	{ IN_FUNC_T9CK, T9CKR },
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	{ IN_FUNC_IC1, IC1R },
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	{ IN_FUNC_IC6, IC6R },
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	{ IN_FUNC_U3CTS, U3CTSR },
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	{ IN_FUNC_U4RX, U4RXR },
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	{ IN_FUNC_U6RX, U6RXR },
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	{ IN_FUNC_SS2, SS2R },
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	{ IN_FUNC_SDI6, SDI6R },
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	{ IN_FUNC_OCFA, OCFAR },
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	{ IN_FUNC_REFCLKI3, REFCLKI3R },
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};
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void pic32_pps_input(int function, int pin)
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{
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	void __iomem *pps_base = ioremap(PPS_BASE, 0xF4);
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	int i;
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	for (i = 0; i < ARRAY_SIZE(input_pin_reg); i++) {
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		if (input_pin_reg[i].function == function) {
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			__raw_writel(pin, pps_base + input_pin_reg[i].reg);
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			return;
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		}
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	}
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	iounmap(pps_base);
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}
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/* Output PPS Registers */
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#define RPA14R 0x1538
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#define RPA15R 0x153C
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#define RPB0R 0x1540
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#define RPB1R 0x1544
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#define RPB2R 0x1548
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#define RPB3R 0x154C
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#define RPB5R 0x1554
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#define RPB6R 0x1558
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#define RPB7R 0x155C
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#define RPB8R 0x1560
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#define RPB9R 0x1564
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#define RPB10R 0x1568
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#define RPB14R 0x1578
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#define RPB15R 0x157C
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#define RPC1R 0x1584
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#define RPC2R 0x1588
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#define RPC3R 0x158C
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#define RPC4R 0x1590
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#define RPC13R 0x15B4
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#define RPC14R 0x15B8
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#define RPD0R 0x15C0
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#define RPD1R 0x15C4
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#define RPD2R 0x15C8
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#define RPD3R 0x15CC
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#define RPD4R 0x15D0
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#define RPD5R 0x15D4
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#define RPD6R 0x15D8
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#define RPD7R 0x15DC
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#define RPD9R 0x15E4
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#define RPD10R 0x15E8
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#define RPD11R 0x15EC
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#define RPD12R 0x15F0
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#define RPD14R 0x15F8
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#define RPD15R 0x15FC
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#define RPE3R 0x160C
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#define RPE5R 0x1614
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#define RPE8R 0x1620
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#define RPE9R 0x1624
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#define RPF0R 0x1640
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#define RPF1R 0x1644
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#define RPF2R 0x1648
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#define RPF3R 0x164C
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#define RPF4R 0x1650
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#define RPF5R 0x1654
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#define RPF8R 0x1660
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#define RPF12R 0x1670
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#define RPF13R 0x1674
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#define RPG0R 0x1680
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#define RPG1R 0x1684
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#define RPG6R 0x1698
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#define RPG7R 0x169C
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#define RPG8R 0x16A0
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#define RPG9R 0x16A4
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static const struct
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{
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	int pin;
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	int reg;
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} output_pin_reg[] = {
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	{ OUT_RPD2, RPD2R },
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	{ OUT_RPG8, RPG8R },
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	{ OUT_RPF4, RPF4R },
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	{ OUT_RPD10, RPD10R },
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	{ OUT_RPF1, RPF1R },
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	{ OUT_RPB9, RPB9R },
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	{ OUT_RPB10, RPB10R },
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	{ OUT_RPC14, RPC14R },
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	{ OUT_RPB5, RPB5R },
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	{ OUT_RPC1, RPC1R },
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	{ OUT_RPD14, RPD14R },
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	{ OUT_RPG1, RPG1R },
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	{ OUT_RPA14, RPA14R },
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	{ OUT_RPD6, RPD6R },
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	{ OUT_RPD3, RPD3R },
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	{ OUT_RPG7, RPG7R },
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	{ OUT_RPF5, RPF5R },
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	{ OUT_RPD11, RPD11R },
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	{ OUT_RPF0, RPF0R },
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	{ OUT_RPB1, RPB1R },
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	{ OUT_RPE5, RPE5R },
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	{ OUT_RPC13, RPC13R },
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	{ OUT_RPB3, RPB3R },
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	{ OUT_RPC4, RPC4R },
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	{ OUT_RPD15, RPD15R },
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	{ OUT_RPG0, RPG0R },
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	{ OUT_RPA15, RPA15R },
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	{ OUT_RPD7, RPD7R },
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	{ OUT_RPD9, RPD9R },
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	{ OUT_RPG6, RPG6R },
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	{ OUT_RPB8, RPB8R },
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	{ OUT_RPB15, RPB15R },
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	{ OUT_RPD4, RPD4R },
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	{ OUT_RPB0, RPB0R },
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	{ OUT_RPE3, RPE3R },
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	{ OUT_RPB7, RPB7R },
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	{ OUT_RPF12, RPF12R },
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	{ OUT_RPD12, RPD12R },
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	{ OUT_RPF8, RPF8R },
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	{ OUT_RPC3, RPC3R },
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	{ OUT_RPE9, RPE9R },
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	{ OUT_RPD1, RPD1R },
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	{ OUT_RPG9, RPG9R },
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	{ OUT_RPB14, RPB14R },
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	{ OUT_RPD0, RPD0R },
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	{ OUT_RPB6, RPB6R },
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	{ OUT_RPD5, RPD5R },
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	{ OUT_RPB2, RPB2R },
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	{ OUT_RPF3, RPF3R },
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	{ OUT_RPF13, RPF13R },
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	{ OUT_RPC2, RPC2R },
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	{ OUT_RPE8, RPE8R },
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	{ OUT_RPF2, RPF2R },
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};
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void pic32_pps_output(int function, int pin)
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{
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	void __iomem *pps_base = ioremap(PPS_BASE, 0x170);
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	int i;
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	for (i = 0; i < ARRAY_SIZE(output_pin_reg); i++) {
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		if (output_pin_reg[i].pin == pin) {
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			__raw_writel(function,
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				pps_base + output_pin_reg[i].reg);
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			return;
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		}
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	}
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	iounmap(pps_base);
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}
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