/* SPDX-License-Identifier: GPL-2.0-or-later */1/*2* OpenRISC Linux3*4* Linux architectural port borrowing liberally from similar works of5* others. All original copyrights apply as per the original source6* declaration.7*8* OpenRISC implementation:9* Copyright (C) 2003 Matjaz Breskvar <[email protected]>10* Copyright (C) 2010-2011 Jonas Bonn <[email protected]>11* et al.12*/1314#ifndef __ASM_OPENRISC_CPUINFO_H15#define __ASM_OPENRISC_CPUINFO_H1617#include <asm/spr.h>18#include <asm/spr_defs.h>1920struct cache_desc {21u32 size;22u32 sets;23u32 block_size;24u32 ways;25};2627struct cpuinfo_or1k {28u32 clock_frequency;2930struct cache_desc icache;31struct cache_desc dcache;3233u16 coreid;34};3536extern struct cpuinfo_or1k cpuinfo_or1k[NR_CPUS];37extern void setup_cpuinfo(void);3839/*40* Check if the cache component exists.41*/42extern bool cpu_cache_is_present(const unsigned int cache_type);4344#endif /* __ASM_OPENRISC_CPUINFO_H */454647