CoCalc -- assembly.h

GitHub Repository: torvalds/linux
Path: blob/master/arch/parisc/include/asm/assembly.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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 * Copyright (C) 1999 Hewlett-Packard (Frank Rowand)
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 * Copyright (C) 1999 Philipp Rumpf <[email protected]>
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 * Copyright (C) 1999 SuSE GmbH
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 * Copyright (C) 2021 Helge Deller <[email protected]>
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 */
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#ifndef _PARISC_ASSEMBLY_H
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#define _PARISC_ASSEMBLY_H
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#ifdef CONFIG_64BIT
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#define RP_OFFSET	16
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#define FRAME_SIZE	128
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#define CALLEE_REG_FRAME_SIZE	144
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#define REG_SZ		8
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#define ASM_ULONG_INSN	.dword
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#else	/* CONFIG_64BIT */
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#define RP_OFFSET	20
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#define FRAME_SIZE	64
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#define CALLEE_REG_FRAME_SIZE	128
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#define REG_SZ		4
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#define ASM_ULONG_INSN	.word
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#endif
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/* Frame alignment for 32- and 64-bit */
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#define FRAME_ALIGN     64
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#define CALLEE_FLOAT_FRAME_SIZE	80
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#define CALLEE_SAVE_FRAME_SIZE (CALLEE_REG_FRAME_SIZE + CALLEE_FLOAT_FRAME_SIZE)
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#ifdef CONFIG_PA20
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#define LDCW		ldcw,co
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#define BL		b,l
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# ifdef CONFIG_64BIT
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#  define PA_ASM_LEVEL	2.0w
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# else
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#  define PA_ASM_LEVEL	2.0
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# endif
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#else
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#define LDCW		ldcw
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#define BL		bl
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#define PA_ASM_LEVEL	1.1
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#endif
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/* Privilege level field in the rightmost two bits of the IA queues */
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#define PRIV_USER	3
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#define PRIV_KERNEL	0
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/* Space register used inside kernel */
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#define SR_KERNEL	0
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#define SR_TEMP1	1
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#define SR_TEMP2	2
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#define SR_USER		3
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#ifdef __ASSEMBLER__
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#ifdef CONFIG_64BIT
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#define LDREG	ldd
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#define STREG	std
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#define LDREGX  ldd,s
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#define LDREGM	ldd,mb
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#define STREGM	std,ma
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#define SHRREG	shrd
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#define SHLREG	shld
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#define ANDCM   andcm,*
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#define	COND(x)	* ## x
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#else	/* CONFIG_64BIT */
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#define LDREG	ldw
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#define STREG	stw
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#define LDREGX  ldwx,s
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#define LDREGM	ldwm
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#define STREGM	stwm
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#define SHRREG	shr
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#define SHLREG	shlw
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#define ANDCM   andcm
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#define COND(x)	x
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#endif
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#ifdef CONFIG_64BIT
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/* the 64-bit pa gnu assembler unfortunately defaults to .level 1.1 or 2.0 so
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 * work around that for now... */
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	.level 2.0w
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#endif
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#include <asm/asm-offsets.h>
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#include <asm/page.h>
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#include <asm/types.h>
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#include <asm/asmregs.h>
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#include <asm/psw.h>
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	/*
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	 * We provide two versions of each macro to convert from physical
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	 * to virtual and vice versa. The "_r1" versions take one argument
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	 * register, but trashes r1 to do the conversion. The other
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	 * version takes two arguments: a src and destination register.
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	 * However, the source and destination registers can not be
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	 * the same register.
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	 *
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	 * We use add,l to avoid clobbering the C/B bits in the PSW.
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	 */
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	.macro  tophys  grvirt, grphys
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	ldil    L%(-__PAGE_OFFSET), \grphys
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	addl    \grvirt, \grphys, \grphys
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	.endm
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	.macro  tovirt  grphys, grvirt
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	ldil    L%(__PAGE_OFFSET), \grvirt
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	addl    \grphys, \grvirt, \grvirt
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	.endm
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	.macro  tophys_r1  gr
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	ldil    L%(-__PAGE_OFFSET), %r1
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	addl    \gr, %r1, \gr
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	.endm
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	.macro  tovirt_r1  gr
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	ldil    L%(__PAGE_OFFSET), %r1
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	addl    \gr, %r1, \gr
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	.endm
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	.macro delay value
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	ldil	L%\value, 1
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	ldo	R%\value(1), 1
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	addib,UV,n -1,1,.
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	addib,NUV,n -1,1,.+8
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	nop
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	.endm
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	.macro	debug value
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	.endm
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	.macro shlw r, sa, t
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	zdep	\r, 31-(\sa), 32-(\sa), \t
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	.endm
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	/* And the PA 2.0W shift left */
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	.macro shld r, sa, t
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	depd,z	\r, 63-(\sa), 64-(\sa), \t
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	.endm
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	/* Shift Right for 32-bit. Clobbers upper 32-bit on PA2.0. */
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	.macro shr r, sa, t
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	extru \r, 31-(\sa), 32-(\sa), \t
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	.endm
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	/* pa20w version of shift right */
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	.macro shrd r, sa, t
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	extrd,u \r, 63-(\sa), 64-(\sa), \t
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	.endm
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	/* Extract unsigned for 32- and 64-bit
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	 * The extru instruction leaves the most significant 32 bits of the
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	 * target register in an undefined state on PA 2.0 systems. */
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	.macro extru_safe r, p, len, t
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#ifdef CONFIG_64BIT
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	extrd,u	\r, 32+(\p), \len, \t
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#else
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	extru	\r, \p, \len, \t
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#endif
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	.endm
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	/* The depi instruction leaves the most significant 32 bits of the
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	 * target register in an undefined state on PA 2.0 systems. */
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	.macro depi_safe i, p, len, t
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#ifdef CONFIG_64BIT
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	depdi	\i, 32+(\p), \len, \t
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#else
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	depi	\i, \p, \len, \t
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#endif
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	.endm
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	/* The depw instruction leaves the most significant 32 bits of the
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	 * target register in an undefined state on PA 2.0 systems. */
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	.macro dep_safe i, p, len, t
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#ifdef CONFIG_64BIT
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	depd	\i, 32+(\p), \len, \t
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#else
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	depw	\i, \p, \len, \t
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#endif
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	.endm
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	/* load 32-bit 'value' into 'reg' compensating for the ldil
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	 * sign-extension when running in wide mode.
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	 * WARNING!! neither 'value' nor 'reg' can be expressions
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	 * containing '.'!!!! */
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	.macro	load32 value, reg
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	ldil	L%\value, \reg
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	ldo	R%\value(\reg), \reg
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	.endm
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	.macro loadgp
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#ifdef CONFIG_64BIT
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	ldil		L%__gp, %r27
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	ldo		R%__gp(%r27), %r27
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#else
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	ldil		L%$global$, %r27
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	ldo		R%$global$(%r27), %r27
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#endif
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	.endm
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#define SAVE_SP(r, where) mfsp r, %r1 ! STREG %r1, where
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#define REST_SP(r, where) LDREG where, %r1 ! mtsp %r1, r
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#define SAVE_CR(r, where) mfctl r, %r1 ! STREG %r1, where
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#define REST_CR(r, where) LDREG where, %r1 ! mtctl %r1, r
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	.macro	save_general	regs
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	STREG %r1, PT_GR1 (\regs)
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	STREG %r2, PT_GR2 (\regs)
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	STREG %r3, PT_GR3 (\regs)
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	STREG %r4, PT_GR4 (\regs)
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	STREG %r5, PT_GR5 (\regs)
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	STREG %r6, PT_GR6 (\regs)
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	STREG %r7, PT_GR7 (\regs)
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	STREG %r8, PT_GR8 (\regs)
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	STREG %r9, PT_GR9 (\regs)
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	STREG %r10, PT_GR10(\regs)
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	STREG %r11, PT_GR11(\regs)
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	STREG %r12, PT_GR12(\regs)
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	STREG %r13, PT_GR13(\regs)
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	STREG %r14, PT_GR14(\regs)
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	STREG %r15, PT_GR15(\regs)
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	STREG %r16, PT_GR16(\regs)
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	STREG %r17, PT_GR17(\regs)
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	STREG %r18, PT_GR18(\regs)
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	STREG %r19, PT_GR19(\regs)
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	STREG %r20, PT_GR20(\regs)
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	STREG %r21, PT_GR21(\regs)
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	STREG %r22, PT_GR22(\regs)
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	STREG %r23, PT_GR23(\regs)
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	STREG %r24, PT_GR24(\regs)
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	STREG %r25, PT_GR25(\regs)
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	/* r26 is saved in get_stack and used to preserve a value across virt_map */
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	STREG %r27, PT_GR27(\regs)
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	STREG %r28, PT_GR28(\regs)
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	/* r29 is saved in get_stack and used to point to saved registers */
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	/* r30 stack pointer saved in get_stack */
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	STREG %r31, PT_GR31(\regs)
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	.endm
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	.macro	rest_general	regs
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	/* r1 used as a temp in rest_stack and is restored there */
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	LDREG PT_GR2 (\regs), %r2
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	LDREG PT_GR3 (\regs), %r3
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	LDREG PT_GR4 (\regs), %r4
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	LDREG PT_GR5 (\regs), %r5
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	LDREG PT_GR6 (\regs), %r6
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	LDREG PT_GR7 (\regs), %r7
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	LDREG PT_GR8 (\regs), %r8
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	LDREG PT_GR9 (\regs), %r9
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	LDREG PT_GR10(\regs), %r10
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	LDREG PT_GR11(\regs), %r11
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	LDREG PT_GR12(\regs), %r12
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	LDREG PT_GR13(\regs), %r13
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	LDREG PT_GR14(\regs), %r14
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	LDREG PT_GR15(\regs), %r15
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	LDREG PT_GR16(\regs), %r16
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	LDREG PT_GR17(\regs), %r17
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	LDREG PT_GR18(\regs), %r18
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	LDREG PT_GR19(\regs), %r19
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	LDREG PT_GR20(\regs), %r20
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	LDREG PT_GR21(\regs), %r21
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	LDREG PT_GR22(\regs), %r22
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	LDREG PT_GR23(\regs), %r23
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	LDREG PT_GR24(\regs), %r24
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	LDREG PT_GR25(\regs), %r25
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	LDREG PT_GR26(\regs), %r26
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	LDREG PT_GR27(\regs), %r27
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	LDREG PT_GR28(\regs), %r28
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	/* r29 points to register save area, and is restored in rest_stack */
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	/* r30 stack pointer restored in rest_stack */
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	LDREG PT_GR31(\regs), %r31
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	.endm
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	.macro	save_fp 	regs
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	fstd,ma  %fr0, 8(\regs)
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	fstd,ma	 %fr1, 8(\regs)
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	fstd,ma	 %fr2, 8(\regs)
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	fstd,ma	 %fr3, 8(\regs)
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	fstd,ma	 %fr4, 8(\regs)
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	fstd,ma	 %fr5, 8(\regs)
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	fstd,ma	 %fr6, 8(\regs)
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	fstd,ma	 %fr7, 8(\regs)
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	fstd,ma	 %fr8, 8(\regs)
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	fstd,ma	 %fr9, 8(\regs)
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	fstd,ma	%fr10, 8(\regs)
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	fstd,ma	%fr11, 8(\regs)
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	fstd,ma	%fr12, 8(\regs)
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	fstd,ma	%fr13, 8(\regs)
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	fstd,ma	%fr14, 8(\regs)
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	fstd,ma	%fr15, 8(\regs)
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	fstd,ma	%fr16, 8(\regs)
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	fstd,ma	%fr17, 8(\regs)
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	fstd,ma	%fr18, 8(\regs)
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	fstd,ma	%fr19, 8(\regs)
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	fstd,ma	%fr20, 8(\regs)
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	fstd,ma	%fr21, 8(\regs)
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	fstd,ma	%fr22, 8(\regs)
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	fstd,ma	%fr23, 8(\regs)
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	fstd,ma	%fr24, 8(\regs)
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	fstd,ma	%fr25, 8(\regs)
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	fstd,ma	%fr26, 8(\regs)
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	fstd,ma	%fr27, 8(\regs)
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	fstd,ma	%fr28, 8(\regs)
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	fstd,ma	%fr29, 8(\regs)
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	fstd,ma	%fr30, 8(\regs)
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	fstd	%fr31, 0(\regs)
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	.endm
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	.macro	rest_fp 	regs
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	fldd	0(\regs),	 %fr31
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	fldd,mb	-8(\regs),       %fr30
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	fldd,mb	-8(\regs),       %fr29
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	fldd,mb	-8(\regs),       %fr28
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	fldd,mb	-8(\regs),       %fr27
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	fldd,mb	-8(\regs),       %fr26
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	fldd,mb	-8(\regs),       %fr25
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	fldd,mb	-8(\regs),       %fr24
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	fldd,mb	-8(\regs),       %fr23
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	fldd,mb	-8(\regs),       %fr22
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	fldd,mb	-8(\regs),       %fr21
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	fldd,mb	-8(\regs),       %fr20
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	fldd,mb	-8(\regs),       %fr19
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	fldd,mb	-8(\regs),       %fr18
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	fldd,mb	-8(\regs),       %fr17
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	fldd,mb	-8(\regs),       %fr16
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	fldd,mb	-8(\regs),       %fr15
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	fldd,mb	-8(\regs),       %fr14
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	fldd,mb	-8(\regs),       %fr13
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	fldd,mb	-8(\regs),       %fr12
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	fldd,mb	-8(\regs),       %fr11
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	fldd,mb	-8(\regs),       %fr10
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	fldd,mb	-8(\regs),       %fr9
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	fldd,mb	-8(\regs),       %fr8
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	fldd,mb	-8(\regs),       %fr7
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	fldd,mb	-8(\regs),       %fr6
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	fldd,mb	-8(\regs),       %fr5
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	fldd,mb	-8(\regs),       %fr4
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	fldd,mb	-8(\regs),       %fr3
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	fldd,mb	-8(\regs),       %fr2
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	fldd,mb	-8(\regs),       %fr1
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	fldd,mb	-8(\regs),       %fr0
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	.endm
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	.macro	callee_save_float
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	fstd,ma	 %fr12,	8(%r30)
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	fstd,ma	 %fr13,	8(%r30)
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	fstd,ma	 %fr14,	8(%r30)
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	fstd,ma	 %fr15,	8(%r30)
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	fstd,ma	 %fr16,	8(%r30)
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	fstd,ma	 %fr17,	8(%r30)
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	fstd,ma	 %fr18,	8(%r30)
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	fstd,ma	 %fr19,	8(%r30)
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	fstd,ma	 %fr20,	8(%r30)
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	fstd,ma	 %fr21,	8(%r30)
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	.endm
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	.macro	callee_rest_float
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	fldd,mb	-8(%r30),   %fr21
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	fldd,mb	-8(%r30),   %fr20
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	fldd,mb	-8(%r30),   %fr19
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	fldd,mb	-8(%r30),   %fr18
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	fldd,mb	-8(%r30),   %fr17
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	fldd,mb	-8(%r30),   %fr16
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	fldd,mb	-8(%r30),   %fr15
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	fldd,mb	-8(%r30),   %fr14
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	fldd,mb	-8(%r30),   %fr13
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	fldd,mb	-8(%r30),   %fr12
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	.endm
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#ifdef CONFIG_64BIT
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	.macro	callee_save
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	std,ma	  %r3,	 CALLEE_REG_FRAME_SIZE(%r30)
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	mfctl	  %cr27, %r3
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	std	  %r4,	-136(%r30)
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	std	  %r5,	-128(%r30)
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	std	  %r6,	-120(%r30)
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	std	  %r7,	-112(%r30)
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	std	  %r8,	-104(%r30)
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	std	  %r9,	 -96(%r30)
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	std	 %r10,	 -88(%r30)
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	std	 %r11,	 -80(%r30)
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	std	 %r12,	 -72(%r30)
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	std	 %r13,	 -64(%r30)
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	std	 %r14,	 -56(%r30)
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	std	 %r15,	 -48(%r30)
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	std	 %r16,	 -40(%r30)
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	std	 %r17,	 -32(%r30)
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	std	 %r18,	 -24(%r30)
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	std	  %r3,	 -16(%r30)
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	.endm
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	.macro	callee_rest
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	ldd	 -16(%r30),    %r3
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	ldd	 -24(%r30),   %r18
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	ldd	 -32(%r30),   %r17
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	ldd	 -40(%r30),   %r16
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	ldd	 -48(%r30),   %r15
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	ldd	 -56(%r30),   %r14
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	ldd	 -64(%r30),   %r13
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	ldd	 -72(%r30),   %r12
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	ldd	 -80(%r30),   %r11
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	ldd	 -88(%r30),   %r10
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	ldd	 -96(%r30),    %r9
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	ldd	-104(%r30),    %r8
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	ldd	-112(%r30),    %r7
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	ldd	-120(%r30),    %r6
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	ldd	-128(%r30),    %r5
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	ldd	-136(%r30),    %r4
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	mtctl	%r3, %cr27
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	ldd,mb	-CALLEE_REG_FRAME_SIZE(%r30),    %r3
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	.endm
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#else /* ! CONFIG_64BIT */
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	.macro	callee_save
419
	stw,ma	 %r3,	CALLEE_REG_FRAME_SIZE(%r30)
420
	mfctl	 %cr27, %r3
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	stw	 %r4,	-124(%r30)
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	stw	 %r5,	-120(%r30)
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	stw	 %r6,	-116(%r30)
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	stw	 %r7,	-112(%r30)
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	stw	 %r8,	-108(%r30)
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	stw	 %r9,	-104(%r30)
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	stw	 %r10,	-100(%r30)
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	stw	 %r11,	 -96(%r30)
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	stw	 %r12,	 -92(%r30)
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	stw	 %r13,	 -88(%r30)
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	stw	 %r14,	 -84(%r30)
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	stw	 %r15,	 -80(%r30)
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	stw	 %r16,	 -76(%r30)
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	stw	 %r17,	 -72(%r30)
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	stw	 %r18,	 -68(%r30)
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	stw	  %r3,	 -64(%r30)
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	.endm
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	.macro	callee_rest
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	ldw	 -64(%r30),    %r3
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	ldw	 -68(%r30),   %r18
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	ldw	 -72(%r30),   %r17
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	ldw	 -76(%r30),   %r16
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	ldw	 -80(%r30),   %r15
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	ldw	 -84(%r30),   %r14
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	ldw	 -88(%r30),   %r13
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	ldw	 -92(%r30),   %r12
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	ldw	 -96(%r30),   %r11
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	ldw	-100(%r30),   %r10
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	ldw	-104(%r30),   %r9
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	ldw	-108(%r30),   %r8
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	ldw	-112(%r30),   %r7
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	ldw	-116(%r30),   %r6
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	ldw	-120(%r30),   %r5
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	ldw	-124(%r30),   %r4
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	mtctl	%r3, %cr27
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	ldw,mb	-CALLEE_REG_FRAME_SIZE(%r30),   %r3
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	.endm
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#endif /* ! CONFIG_64BIT */
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	.macro	save_specials	regs
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463
	SAVE_SP  (%sr0, PT_SR0 (\regs))
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	SAVE_SP  (%sr1, PT_SR1 (\regs))
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	SAVE_SP  (%sr2, PT_SR2 (\regs))
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	SAVE_SP  (%sr3, PT_SR3 (\regs))
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	SAVE_SP  (%sr4, PT_SR4 (\regs))
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	SAVE_SP  (%sr5, PT_SR5 (\regs))
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	SAVE_SP  (%sr6, PT_SR6 (\regs))
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	SAVE_CR  (%cr17, PT_IASQ0(\regs))
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	mtctl	 %r0,	%cr17
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	SAVE_CR  (%cr17, PT_IASQ1(\regs))
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	SAVE_CR  (%cr18, PT_IAOQ0(\regs))
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	mtctl	 %r0,	%cr18
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	SAVE_CR  (%cr18, PT_IAOQ1(\regs))
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#ifdef CONFIG_64BIT
480
	/* cr11 (sar) is a funny one.  5 bits on PA1.1 and 6 bit on PA2.0
481
	 * For PA2.0 mtsar or mtctl always write 6 bits, but mfctl only
482
	 * reads 5 bits.  Use mfctl,w to read all six bits.  Otherwise
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	 * we lose the 6th bit on a save/restore over interrupt.
484
	 */
485
	mfctl,w  %cr11, %r1
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	STREG    %r1, PT_SAR (\regs)
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#else
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	SAVE_CR  (%cr11, PT_SAR  (\regs))
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#endif
490
	SAVE_CR  (%cr19, PT_IIR  (\regs))
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492
	/*
493
	 * Code immediately following this macro (in intr_save) relies
494
	 * on r8 containing ipsw.
495
	 */
496
	mfctl    %cr22, %r8
497
	STREG    %r8,   PT_PSW(\regs)
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	.endm
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500
	.macro	rest_specials	regs
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502
	REST_SP  (%sr0, PT_SR0 (\regs))
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	REST_SP  (%sr1, PT_SR1 (\regs))
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	REST_SP  (%sr2, PT_SR2 (\regs))
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	REST_SP  (%sr3, PT_SR3 (\regs))
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	REST_SP  (%sr4, PT_SR4 (\regs))
507
	REST_SP  (%sr5, PT_SR5 (\regs))
508
	REST_SP  (%sr6, PT_SR6 (\regs))
509
	REST_SP  (%sr7, PT_SR7 (\regs))
510

511
	REST_CR	(%cr17, PT_IASQ0(\regs))
512
	REST_CR	(%cr17, PT_IASQ1(\regs))
513

514
	REST_CR	(%cr18, PT_IAOQ0(\regs))
515
	REST_CR	(%cr18, PT_IAOQ1(\regs))
516

517
	REST_CR (%cr11, PT_SAR	(\regs))
518

519
	REST_CR	(%cr22, PT_PSW	(\regs))
520
	.endm
521

522

523
	/* First step to create a "relied upon translation"
524
	 * See PA 2.0 Arch. page F-4 and F-5.
525
	 *
526
	 * The ssm was originally necessary due to a "PCxT bug".
527
	 * But someone decided it needed to be added to the architecture
528
	 * and this "feature" went into rev3 of PA-RISC 1.1 Arch Manual.
529
	 * It's been carried forward into PA 2.0 Arch as well. :^(
530
	 *
531
	 * "ssm 0,%r0" is a NOP with side effects (prefetch barrier).
532
	 * rsm/ssm prevents the ifetch unit from speculatively fetching
533
	 * instructions past this line in the code stream.
534
	 * PA 2.0 processor will single step all insn in the same QUAD (4 insn).
535
	 */
536
	.macro	pcxt_ssm_bug
537
	rsm	PSW_SM_I,%r0
538
	nop	/* 1 */
539
	nop	/* 2 */
540
	nop	/* 3 */
541
	nop	/* 4 */
542
	nop	/* 5 */
543
	nop	/* 6 */
544
	nop	/* 7 */
545
	.endm
546

547
	/* Switch to virtual mapping, trashing only %r1 */
548
	.macro  virt_map
549
	/* pcxt_ssm_bug */
550
	rsm	PSW_SM_I, %r0		/* barrier for "Relied upon Translation */
551
	mtsp	%r0, %sr4
552
	mtsp	%r0, %sr5
553
	mtsp	%r0, %sr6
554
	tovirt_r1 %r29
555
	load32	KERNEL_PSW, %r1
556

557
	rsm     PSW_SM_QUIET,%r0	/* second "heavy weight" ctl op */
558
	mtctl	%r0, %cr17		/* Clear IIASQ tail */
559
	mtctl	%r0, %cr17		/* Clear IIASQ head */
560
	mtctl	%r1, %ipsw
561
	load32	4f, %r1
562
	mtctl	%r1, %cr18		/* Set IIAOQ tail */
563
	ldo	4(%r1), %r1
564
	mtctl	%r1, %cr18		/* Set IIAOQ head */
565
	rfir
566
	nop
567
4:
568
	.endm
569

570

571
	/*
572
	 * ASM_EXCEPTIONTABLE_ENTRY
573
	 *
574
	 * Creates an exception table entry.
575
	 * Do not convert to a assembler macro. This won't work.
576
	 */
577
#define ASM_EXCEPTIONTABLE_ENTRY(fault_addr, except_addr)	\
578
	.section __ex_table,"aw"			!	\
579
	.align 4					!	\
580
	.word (fault_addr - .), (except_addr - .)	!	\
581
	or %r0,%r0,%r0					!	\
582
	.previous
583

584

585
#endif /* __ASSEMBLER__ */
586
#endif
587

588
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