CoCalc -- bpf

GitHub Repository: torvalds/linux
Path: blob/master/arch/parisc/net/bpf_jit.h
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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 * Common functionality for PARISC32 and PARISC64 BPF JIT compilers
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 *
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 * Copyright (c) 2023 Helge Deller <[email protected]>
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 *
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 */
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#ifndef _BPF_JIT_H
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#define _BPF_JIT_H
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#include <linux/bpf.h>
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#include <linux/filter.h>
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#include <asm/cacheflush.h>
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#define HPPA_JIT_DEBUG	0
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#define HPPA_JIT_REBOOT	0
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#define HPPA_JIT_DUMP	0
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#define OPTIMIZE_HPPA	1	/* enable some asm optimizations */
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// echo 1 > /proc/sys/net/core/bpf_jit_enable
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#define HPPA_R(nr)	nr	/* use HPPA register #nr */
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enum {
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	HPPA_REG_ZERO =	0,	/* The constant value 0 */
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	HPPA_REG_R1 =	1,	/* used for addil */
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	HPPA_REG_RP =	2,	/* Return address */
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	HPPA_REG_ARG7 =	19,	/* ARG4-7 used in 64-bit ABI */
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	HPPA_REG_ARG6 =	20,
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	HPPA_REG_ARG5 =	21,
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	HPPA_REG_ARG4 =	22,
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	HPPA_REG_ARG3 =	23,	/* ARG0-3 in 32- and 64-bit ABI */
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	HPPA_REG_ARG2 =	24,
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	HPPA_REG_ARG1 =	25,
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	HPPA_REG_ARG0 =	26,
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	HPPA_REG_GP =	27,	/* Global pointer */
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	HPPA_REG_RET0 =	28,	/* Return value, HI in 32-bit */
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	HPPA_REG_RET1 =	29,	/* Return value, LOW in 32-bit */
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	HPPA_REG_SP =	30,	/* Stack pointer */
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	HPPA_REG_R31 =	31,
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#ifdef CONFIG_64BIT
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	HPPA_REG_TCC	     = 3,
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	HPPA_REG_TCC_SAVED   = 4,
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	HPPA_REG_TCC_IN_INIT = HPPA_REG_R31,
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#else
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	HPPA_REG_TCC	     = 18,
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	HPPA_REG_TCC_SAVED   = 17,
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	HPPA_REG_TCC_IN_INIT = HPPA_REG_R31,
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#endif
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	HPPA_REG_T0 =	HPPA_REG_R1,	/* Temporaries */
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	HPPA_REG_T1 =	HPPA_REG_R31,
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	HPPA_REG_T2 =	HPPA_REG_ARG4,
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#ifndef CONFIG_64BIT
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	HPPA_REG_T3 =	HPPA_REG_ARG5,	/* not used in 64-bit */
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	HPPA_REG_T4 =	HPPA_REG_ARG6,
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	HPPA_REG_T5 =	HPPA_REG_ARG7,
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#endif
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};
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struct hppa_jit_context {
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	struct bpf_prog *prog;
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	u32 *insns;		/* HPPA insns */
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	int ninsns;
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	int reg_seen_collect;
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	int reg_seen;
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	int body_len;
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	int epilogue_offset;
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	int prologue_len;
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	int *offset;		/* BPF to HPPA */
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};
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#define REG_SET_SEEN(ctx, nr)	{ if (ctx->reg_seen_collect) ctx->reg_seen |= BIT(nr); }
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#define REG_SET_SEEN_ALL(ctx)	{ if (ctx->reg_seen_collect) ctx->reg_seen = -1; }
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#define REG_FORCE_SEEN(ctx, nr)	{ ctx->reg_seen |= BIT(nr); }
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#define REG_WAS_SEEN(ctx, nr)	(ctx->reg_seen & BIT(nr))
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#define REG_ALL_SEEN(ctx)	(ctx->reg_seen == -1)
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#define HPPA_INSN_SIZE		4	/* bytes per HPPA asm instruction */
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#define REG_SIZE		REG_SZ	/* bytes per native "long" word */
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/* subtract hppa displacement on branches which is .+8 */
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#define HPPA_BRANCH_DISPLACEMENT  2	/* instructions */
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/* asm statement indicator to execute delay slot */
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#define EXEC_NEXT_INSTR	0
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#define NOP_NEXT_INSTR	1
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#define im11(val)	(((u32)(val)) & 0x07ff)
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#define hppa_ldil(addr, reg) \
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	hppa_t5_insn(0x08, reg, ((u32)(addr)) >> 11)		/* ldil im21,reg */
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#define hppa_addil(addr, reg) \
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	hppa_t5_insn(0x0a, reg, ((u32)(addr)) >> 11)		/* addil im21,reg -> result in gr1 */
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#define hppa_ldo(im14, reg, target) \
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	hppa_t1_insn(0x0d, reg, target, im14)			/* ldo val14(reg),target */
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#define hppa_ldi(im14, reg) \
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	hppa_ldo(im14, HPPA_REG_ZERO, reg)			/* ldi val14,reg */
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#define hppa_or(reg1, reg2, target) \
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	hppa_t6_insn(0x02, reg2, reg1, 0, 0, 0x09, target)	/* or reg1,reg2,target */
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#define hppa_or_cond(reg1, reg2, cond, f, target) \
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	hppa_t6_insn(0x02, reg2, reg1, cond, f, 0x09, target)
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#define hppa_and(reg1, reg2, target) \
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	hppa_t6_insn(0x02, reg2, reg1, 0, 0, 0x08, target)	/* and reg1,reg2,target */
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#define hppa_and_cond(reg1, reg2, cond, f, target) \
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	hppa_t6_insn(0x02, reg2, reg1, cond, f, 0x08, target)
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#define hppa_xor(reg1, reg2, target) \
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	hppa_t6_insn(0x02, reg2, reg1, 0, 0, 0x0a, target)	/* xor reg1,reg2,target */
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#define hppa_add(reg1, reg2, target) \
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	hppa_t6_insn(0x02, reg2, reg1, 0, 0, 0x18, target)	/* add reg1,reg2,target */
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#define hppa_addc(reg1, reg2, target) \
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	hppa_t6_insn(0x02, reg2, reg1, 0, 0, 0x1c, target)	/* add,c reg1,reg2,target */
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#define hppa_sub(reg1, reg2, target) \
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	hppa_t6_insn(0x02, reg2, reg1, 0, 0, 0x10, target)	/* sub reg1,reg2,target */
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#define hppa_subb(reg1, reg2, target) \
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	hppa_t6_insn(0x02, reg2, reg1, 0, 0, 0x14, target)	/* sub,b reg1,reg2,target */
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#define hppa_nop() \
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	hppa_or(0,0,0)						/* nop: or 0,0,0 */
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#define hppa_addi(val11, reg, target) \
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	hppa_t7_insn(0x2d, reg, target, val11)			/* addi im11,reg,target */
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#define hppa_subi(val11, reg, target) \
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	hppa_t7_insn(0x25, reg, target, val11)			/* subi im11,reg,target */
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#define hppa_copy(reg, target) \
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	hppa_or(reg, HPPA_REG_ZERO, target)			/* copy reg,target */
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#define hppa_ldw(val14, reg, target) \
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	hppa_t1_insn(0x12, reg, target, val14)			/* ldw im14(reg),target */
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#define hppa_ldb(val14, reg, target) \
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	hppa_t1_insn(0x10, reg, target, val14)			/* ldb im14(reg),target */
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#define hppa_ldh(val14, reg, target) \
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	hppa_t1_insn(0x11, reg, target, val14)			/* ldh im14(reg),target */
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#define hppa_stw(reg, val14, base) \
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	hppa_t1_insn(0x1a, base, reg, val14)			/* stw reg,im14(base) */
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#define hppa_stb(reg, val14, base) \
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	hppa_t1_insn(0x18, base, reg, val14)			/* stb reg,im14(base) */
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#define hppa_sth(reg, val14, base) \
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	hppa_t1_insn(0x19, base, reg, val14)			/* sth reg,im14(base) */
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#define hppa_stwma(reg, val14, base) \
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	hppa_t1_insn(0x1b, base, reg, val14)			/* stw,ma reg,im14(base) */
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#define hppa_bv(reg, base, nop) \
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	hppa_t11_insn(0x3a, base, reg, 0x06, 0, nop)		/* bv(,n) reg(base) */
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#define hppa_be(offset, base) \
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	hppa_t12_insn(0x38, base, offset, 0x00, 1)		/* be,n offset(0,base) */
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#define hppa_be_l(offset, base, nop) \
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	hppa_t12_insn(0x39, base, offset, 0x00, nop)		/* ble(,nop) offset(0,base) */
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#define hppa_mtctl(reg, cr) \
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	hppa_t21_insn(0x00, cr, reg, 0xc2, 0)			/* mtctl reg,cr */
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#define hppa_mtsar(reg) \
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	hppa_mtctl(reg, 11)					/* mtsar reg */
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#define hppa_zdep(r, p, len, target) \
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	hppa_t10_insn(0x35, target, r, 0, 2, p, len)		/* zdep r,a,b,t */
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#define hppa_shl(r, len, target) \
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	hppa_zdep(r, len, len, lo(rd))
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#define hppa_depwz(r, p, len, target) \
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	hppa_t10_insn(0x35, target, r, 0, 3, 31-(p), 32-(len))	/* depw,z r,p,len,ret1 */
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#define hppa_depwz_sar(reg, target) \
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	hppa_t1_insn(0x35, target, reg, 0)			/* depw,z reg,sar,32,target */
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#define hppa_shrpw_sar(reg, target) \
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	hppa_t10_insn(0x34, reg, 0, 0, 0, 0, target)		/* shrpw r0,reg,sar,target */
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#define hppa_shrpw(r1, r2, p, target) \
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	hppa_t10_insn(0x34, r2, r1, 0, 2, 31-(p), target)	/* shrpw r1,r2,p,target */
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#define hppa_shd(r1, r2, p, target) \
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	hppa_t10_insn(0x34, r2, r1, 0, 2, 31-(p), target)	/* shrpw r1,r2,p,tarfer */
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#define hppa_extrws_sar(reg, target) \
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	hppa_t10_insn(0x34, reg, target, 0, 5, 0, 0)		/* extrw,s reg,sar,32,ret0 */
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#define hppa_extrws(reg, p, len, target) \
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	hppa_t10_insn(0x34, reg, target, 0, 7, p, len)		/* extrw,s reg,p,len,target */
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#define hppa_extru(r, p, len, target) \
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	hppa_t10_insn(0x34, r, target, 0, 6, p, 32-(len))
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#define hppa_shr(r, len, target) \
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	hppa_extru(r, 31-(len), 32-(len), target)
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#define hppa_bl(imm17, rp) \
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	hppa_t12_insn(0x3a, rp, imm17, 0x00, 1)			/* bl,n target_addr,rp */
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#define hppa_sh2add(r1, r2, target) \
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	hppa_t6_insn(0x02, r2, r1, 0, 0, 0x1a, target)		/* sh2add r1,r2,target */
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#define hppa_combt(r1, r2, target_addr, condition, nop) \
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	hppa_t11_insn(IS_ENABLED(CONFIG_64BIT) ? 0x27 : 0x20, \
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		r2, r1, condition, target_addr, nop)		/* combt,cond,n r1,r2,addr */
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#define hppa_beq(r1, r2, target_addr) \
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	hppa_combt(r1, r2, target_addr, 1, NOP_NEXT_INSTR)
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#define hppa_blt(r1, r2, target_addr) \
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	hppa_combt(r1, r2, target_addr, 2, NOP_NEXT_INSTR)
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#define hppa_ble(r1, r2, target_addr) \
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	hppa_combt(r1, r2, target_addr, 3, NOP_NEXT_INSTR)
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#define hppa_bltu(r1, r2, target_addr) \
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	hppa_combt(r1, r2, target_addr, 4, NOP_NEXT_INSTR)
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#define hppa_bleu(r1, r2, target_addr) \
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	hppa_combt(r1, r2, target_addr, 5, NOP_NEXT_INSTR)
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#define hppa_combf(r1, r2, target_addr, condition, nop) \
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	hppa_t11_insn(IS_ENABLED(CONFIG_64BIT) ? 0x2f : 0x22, \
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		r2, r1, condition, target_addr, nop)		/* combf,cond,n r1,r2,addr */
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#define hppa_bne(r1, r2, target_addr) \
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	hppa_combf(r1, r2, target_addr, 1, NOP_NEXT_INSTR)
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#define hppa_bge(r1, r2, target_addr) \
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	hppa_combf(r1, r2, target_addr, 2, NOP_NEXT_INSTR)
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#define hppa_bgt(r1, r2, target_addr) \
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	hppa_combf(r1, r2, target_addr, 3, NOP_NEXT_INSTR)
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#define hppa_bgeu(r1, r2, target_addr) \
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	hppa_combf(r1, r2, target_addr, 4, NOP_NEXT_INSTR)
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#define hppa_bgtu(r1, r2, target_addr) \
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	hppa_combf(r1, r2, target_addr, 5, NOP_NEXT_INSTR)
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/* 64-bit instructions */
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#ifdef CONFIG_64BIT
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#define hppa64_ldd_reg(reg, b, target) \
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	hppa_t10_insn(0x03, b, reg, 0, 0, 3<<1, target)
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#define hppa64_ldd_im5(im5, b, target) \
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	hppa_t10_insn(0x03, b, low_sign_unext(im5,5), 0, 1<<2, 3<<1, target)
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#define hppa64_ldd_im16(im16, b, target) \
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	hppa_t10_insn(0x14, b, target, 0, 0, 0, 0) | re_assemble_16(im16)
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#define hppa64_std_im5(src, im5, b) \
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	hppa_t10_insn(0x03, b, src, 0, 1<<2, 0xB<<1, low_sign_unext(im5,5))
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#define hppa64_std_im16(src, im16, b) \
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	hppa_t10_insn(0x1c, b, src, 0, 0, 0, 0) | re_assemble_16(im16)
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#define hppa64_bl_long(offs22) \
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	hppa_t12_L_insn(0x3a, offs22, 1)
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#define hppa64_mtsarcm(reg) \
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	hppa_t21_insn(0x00, 11, reg, 0xc6, 0)
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#define hppa64_shrpd_sar(reg, target) \
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	hppa_t10_insn(0x34, reg, 0, 0, 0, 1<<4, target)
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#define hppa64_shladd(r1, sa, r2, target) \
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	hppa_t6_insn(0x02, r2, r1, 0, 0, 1<<4|1<<3|sa, target)
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#define hppa64_depdz_sar(reg, target) \
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	hppa_t21_insn(0x35, target, reg, 3<<3, 0)
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#define hppa_extrd_sar(reg, target, se) \
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	hppa_t10_insn(0x34, reg, target, 0, 0, 0, 0) | 2<<11 | (se&1)<<10 | 1<<9 | 1<<8
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#define hppa64_bve_l_rp(base) \
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	(0x3a << 26) | (base << 21) | 0xf000
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#define hppa64_permh_3210(r, target) \
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	(0x3e << 26) | (r << 21) | (r << 16) | (target) | 0x00006900
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#define hppa64_hshl(r, sa, target) \
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	(0x3e << 26) | (0 << 21) | (r << 16) | (sa << 6) | (target) | 0x00008800
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#define hppa64_hshr_u(r, sa, target) \
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	(0x3e << 26) | (r << 21) | (0 << 16) | (sa << 6) | (target) | 0x0000c800
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#endif
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struct hppa_jit_data {
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	struct bpf_binary_header *header;
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	u8 *image;
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	struct hppa_jit_context ctx;
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};
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static inline void bpf_fill_ill_insns(void *area, unsigned int size)
249
{
250
	memset(area, 0, size);
251
}
252

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static inline void bpf_flush_icache(void *start, void *end)
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{
255
	flush_icache_range((unsigned long)start, (unsigned long)end);
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}
257

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/* Emit a 4-byte HPPA instruction. */
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static inline void emit(const u32 insn, struct hppa_jit_context *ctx)
260
{
261
	if (ctx->insns) {
262
		ctx->insns[ctx->ninsns] = insn;
263
	}
264

265
	ctx->ninsns++;
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}
267

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static inline int epilogue_offset(struct hppa_jit_context *ctx)
269
{
270
	int to = ctx->epilogue_offset, from = ctx->ninsns;
271

272
	return (to - from);
273
}
274

275
/* Return -1 or inverted cond. */
276
static inline int invert_bpf_cond(u8 cond)
277
{
278
	switch (cond) {
279
	case BPF_JEQ:
280
		return BPF_JNE;
281
	case BPF_JGT:
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		return BPF_JLE;
283
	case BPF_JLT:
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		return BPF_JGE;
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	case BPF_JGE:
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		return BPF_JLT;
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	case BPF_JLE:
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		return BPF_JGT;
289
	case BPF_JNE:
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		return BPF_JEQ;
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	case BPF_JSGT:
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		return BPF_JSLE;
293
	case BPF_JSLT:
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		return BPF_JSGE;
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	case BPF_JSGE:
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		return BPF_JSLT;
297
	case BPF_JSLE:
298
		return BPF_JSGT;
299
	}
300
	return -1;
301
}
302

303

304
static inline signed long hppa_offset(int insn, int off, struct hppa_jit_context *ctx)
305
{
306
	signed long from, to;
307

308
	off++; /* BPF branch is from PC+1 */
309
	from = (insn > 0) ? ctx->offset[insn - 1] : 0;
310
	to = (insn + off > 0) ? ctx->offset[insn + off - 1] : 0;
311
	return (to - from);
312
}
313

314
/* does the signed value fits into a given number of bits ? */
315
static inline int check_bits_int(signed long val, int bits)
316
{
317
	return	((val >= 0) && ((val >> bits) == 0)) ||
318
		 ((val < 0) && (((~((u32)val)) >> (bits-1)) == 0));
319
}
320

321
/* can the signed value be used in relative code ? */
322
static inline int relative_bits_ok(signed long val, int bits)
323
{
324
	return	((val >= 0) && (val < (1UL << (bits-1)))) || /* XXX */
325
		 ((val < 0) && (((~((unsigned long)val)) >> (bits-1)) == 0)
326
			    && (val & (1UL << (bits-1))));
327
}
328

329
/* can the signed value be used in relative branches ? */
330
static inline int relative_branch_ok(signed long val, int bits)
331
{
332
	return	((val >= 0) && (val < (1UL << (bits-2)))) || /* XXX */
333
		 ((val < 0) && (((~((unsigned long)val)) < (1UL << (bits-2))))
334
			    && (val & (1UL << (bits-1))));
335
}
336

337

338
#define is_5b_int(val)		check_bits_int(val, 5)
339

340
static inline unsigned sign_unext(unsigned x, unsigned len)
341
{
342
	unsigned len_ones;
343

344
	len_ones = (1 << len) - 1;
345
	return x & len_ones;
346
}
347

348
static inline unsigned low_sign_unext(unsigned x, unsigned len)
349
{
350
	unsigned temp;
351
	unsigned sign;
352

353
	sign = (x >> (len-1)) & 1;
354
	temp = sign_unext (x, len-1);
355
	return (temp << 1) | sign;
356
}
357

358
static inline unsigned re_assemble_12(unsigned as12)
359
{
360
	return ((  (as12 & 0x800) >> 11)
361
		| ((as12 & 0x400) >> (10 - 2))
362
		| ((as12 & 0x3ff) << (1 + 2)));
363
}
364

365
static inline unsigned re_assemble_14(unsigned as14)
366
{
367
	return ((  (as14 & 0x1fff) << 1)
368
		| ((as14 & 0x2000) >> 13));
369
}
370

371
#ifdef CONFIG_64BIT
372
static inline unsigned re_assemble_16(unsigned as16)
373
{
374
	unsigned s, t;
375

376
	/* Unusual 16-bit encoding, for wide mode only.  */
377
	t = (as16 << 1) & 0xffff;
378
	s = (as16 & 0x8000);
379
	return (t ^ s ^ (s >> 1)) | (s >> 15);
380
}
381
#endif
382

383
static inline unsigned re_assemble_17(unsigned as17)
384
{
385
	return ((  (as17 & 0x10000) >> 16)
386
		| ((as17 & 0x0f800) << (16 - 11))
387
		| ((as17 & 0x00400) >> (10 - 2))
388
		| ((as17 & 0x003ff) << (1 + 2)));
389
}
390

391
static inline unsigned re_assemble_21(unsigned as21)
392
{
393
	return ((  (as21 & 0x100000) >> 20)
394
		| ((as21 & 0x0ffe00) >> 8)
395
		| ((as21 & 0x000180) << 7)
396
		| ((as21 & 0x00007c) << 14)
397
		| ((as21 & 0x000003) << 12));
398
}
399

400
static inline unsigned re_assemble_22(unsigned as22)
401
{
402
	return ((  (as22 & 0x200000) >> 21)
403
		| ((as22 & 0x1f0000) << (21 - 16))
404
		| ((as22 & 0x00f800) << (16 - 11))
405
		| ((as22 & 0x000400) >> (10 - 2))
406
		| ((as22 & 0x0003ff) << (1 + 2)));
407
}
408

409
/* Various HPPA instruction formats. */
410
/* see https://parisc.wiki.kernel.org/images-parisc/6/68/Pa11_acd.pdf, appendix C */
411

412
static inline u32 hppa_t1_insn(u8 opcode, u8 b, u8 r, s16 im14)
413
{
414
	return ((opcode << 26) | (b << 21) | (r << 16) | re_assemble_14(im14));
415
}
416

417
static inline u32 hppa_t5_insn(u8 opcode, u8 tr, u32 val21)
418
{
419
	return ((opcode << 26) | (tr << 21) | re_assemble_21(val21));
420
}
421

422
static inline u32 hppa_t6_insn(u8 opcode, u8 r2, u8 r1, u8 c, u8 f, u8 ext6, u16 t)
423
{
424
	return ((opcode << 26) | (r2 << 21) | (r1 << 16) | (c << 13) | (f << 12) |
425
		(ext6 << 6) | t);
426
}
427

428
/* 7. Arithmetic immediate */
429
static inline u32 hppa_t7_insn(u8 opcode, u8 r, u8 t, u32 im11)
430
{
431
	return ((opcode << 26) | (r << 21) | (t << 16) | low_sign_unext(im11, 11));
432
}
433

434
/* 10. Shift instructions */
435
static inline u32 hppa_t10_insn(u8 opcode, u8 r2, u8 r1, u8 c, u8 ext3, u8 cp, u8 t)
436
{
437
	return ((opcode << 26) | (r2 << 21) | (r1 << 16) | (c << 13) |
438
		(ext3 << 10) | (cp << 5) | t);
439
}
440

441
/* 11. Conditional branch instructions */
442
static inline u32 hppa_t11_insn(u8 opcode, u8 r2, u8 r1, u8 c, u32 w, u8 nop)
443
{
444
	u32 ra = re_assemble_12(w);
445
	// ra = low_sign_unext(w,11) | (w & (1<<10)
446
	return ((opcode << 26) | (r2 << 21) | (r1 << 16) | (c << 13) | (nop << 1) | ra);
447
}
448

449
/* 12. Branch instructions */
450
static inline u32 hppa_t12_insn(u8 opcode, u8 rp, u32 w, u8 ext3, u8 nop)
451
{
452
	return ((opcode << 26) | (rp << 21) | (ext3 << 13) | (nop << 1) | re_assemble_17(w));
453
}
454

455
static inline u32 hppa_t12_L_insn(u8 opcode, u32 w, u8 nop)
456
{
457
	return ((opcode << 26) | (0x05 << 13) | (nop << 1) | re_assemble_22(w));
458
}
459

460
/* 21. Move to control register */
461
static inline u32 hppa_t21_insn(u8 opcode, u8 r2, u8 r1, u8 ext8, u8 t)
462
{
463
	return ((opcode << 26) | (r2 << 21) | (r1 << 16) | (ext8 << 5) | t);
464
}
465

466
/* Helper functions called by jit code on HPPA32 and HPPA64. */
467

468
u64 hppa_div64(u64 div, u64 divisor);
469
u64 hppa_div64_rem(u64 div, u64 divisor);
470

471
/* Helper functions that emit HPPA instructions when possible. */
472

473
void bpf_jit_build_prologue(struct hppa_jit_context *ctx);
474
void bpf_jit_build_epilogue(struct hppa_jit_context *ctx);
475

476
int bpf_jit_emit_insn(const struct bpf_insn *insn, struct hppa_jit_context *ctx,
477
		      bool extra_pass);
478

479
#endif /* _BPF_JIT_H */
480

481
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