Book a Demo!
CoCalc Logo Icon
StoreFeaturesDocsShareSupportNewsAboutPoliciesSign UpSign In
torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/arch/powerpc/kernel/cpu_setup_44x.S
26451 views
1
/* SPDX-License-Identifier: GPL-2.0-or-later */

2
/*

3
 * This file contains low level CPU setup functions.

4
 * Valentine Barshak <[email protected]>

5
 * MontaVista Software, Inc (c) 2007

6
 *

7
 * Based on cpu_setup_6xx code by

8
 * Benjamin Herrenschmidt <[email protected]>

9
 */

10


11
#include <asm/processor.h>

12
#include <asm/cputable.h>

13
#include <asm/ppc_asm.h>

14


15
_GLOBAL(__setup_cpu_440ep)

16
	b	__init_fpu_44x

17
_GLOBAL(__setup_cpu_440epx)

18
	mflr	r4

19
	bl	__init_fpu_44x

20
	bl	__plb_disable_wrp

21
	bl	__fixup_440A_mcheck

22
	mtlr	r4

23
	blr

24
_GLOBAL(__setup_cpu_440grx)

25
	mflr	r4

26
	bl	__plb_disable_wrp

27
	bl	__fixup_440A_mcheck

28
	mtlr	r4

29
	blr

30
_GLOBAL(__setup_cpu_460ex)

31
_GLOBAL(__setup_cpu_460gt)

32
_GLOBAL(__setup_cpu_460sx)

33
_GLOBAL(__setup_cpu_apm821xx)

34
	mflr	r4

35
	bl	__init_fpu_44x

36
	bl	__fixup_440A_mcheck

37
	mtlr	r4

38
	blr

39


40
_GLOBAL(__setup_cpu_440x5)

41
_GLOBAL(__setup_cpu_440gx)

42
_GLOBAL(__setup_cpu_440spe)

43
	b	__fixup_440A_mcheck

44


45
/* enable APU between CPU and FPU */

46
_GLOBAL(__init_fpu_44x)

47
	mfspr	r3,SPRN_CCR0

48
	/* Clear DAPUIB flag in CCR0 */

49
	rlwinm	r3,r3,0,12,10

50
	mtspr	SPRN_CCR0,r3

51
	isync

52
	blr

53


54
/*

55
 * Workaround for the incorrect write to DDR SDRAM errata.

56
 * The write address can be corrupted during writes to

57
 * DDR SDRAM when write pipelining is enabled on PLB0.

58
 * Disable write pipelining here.

59
 */

60
#define DCRN_PLB4A0_ACR	0x81

61


62
_GLOBAL(__plb_disable_wrp)

63
	mfdcr	r3,DCRN_PLB4A0_ACR

64
	/* clear WRP bit in PLB4A0_ACR */

65
	rlwinm	r3,r3,0,8,6

66
	mtdcr	DCRN_PLB4A0_ACR,r3

67
	isync

68
	blr

69


70


71