CoCalc -- cpu_setup

GitHub Repository: torvalds/linux
Path: blob/master/arch/powerpc/kernel/cpu_setup_ppc970.S
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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 * This file contains low level CPU setup functions.
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 *    Copyright (C) 2003 Benjamin Herrenschmidt ([email protected])
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 */
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/cputable.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/cache.h>
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_GLOBAL(__cpu_preinit_ppc970)
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	/* Do nothing if not running in HV mode */
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	mfmsr	r0
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	rldicl.	r0,r0,4,63
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	beqlr
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	/* Make sure HID4:rm_ci is off before MMU is turned off, that large
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	 * pages are enabled with HID4:61 and clear HID5:DCBZ_size and
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	 * HID5:DCBZ32_ill
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	 */
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	li	r0,0
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	mfspr	r3,SPRN_HID4
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	rldimi	r3,r0,40,23	/* clear bit 23 (rm_ci) */
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	rldimi	r3,r0,2,61	/* clear bit 61 (lg_pg_en) */
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	sync
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	mtspr	SPRN_HID4,r3
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	isync
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	sync
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	mfspr	r3,SPRN_HID5
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	rldimi	r3,r0,6,56	/* clear bits 56 & 57 (DCBZ*) */
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	sync
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	mtspr	SPRN_HID5,r3
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	isync
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	sync
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	/* Setup some basic HID1 features */
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	mfspr	r0,SPRN_HID1
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	li	r3,0x1200		/* enable i-fetch cacheability */
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	sldi	r3,r3,44		/* and prefetch */
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	or	r0,r0,r3
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	mtspr	SPRN_HID1,r0
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	mtspr	SPRN_HID1,r0
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	isync
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	/* Clear HIOR */
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	li	r0,0
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	sync
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	mtspr	SPRN_HIOR,0		/* Clear interrupt prefix */
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	isync
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	blr
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/* Definitions for the table use to save CPU states */
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#define CS_HID0		0
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#define CS_HID1		8
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#define	CS_HID4		16
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#define CS_HID5		24
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#define CS_SIZE		32
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	.data
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	.balign	L1_CACHE_BYTES,0
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cpu_state_storage:
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	.space	CS_SIZE
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	.balign	L1_CACHE_BYTES,0
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	.text
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_GLOBAL(__setup_cpu_ppc970)
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	/* Do nothing if not running in HV mode */
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	mfmsr	r0
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	rldicl.	r0,r0,4,63
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	beq	no_hv_mode
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	mfspr	r0,SPRN_HID0
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	li	r11,5			/* clear DOZE and SLEEP */
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	rldimi	r0,r11,52,8		/* set NAP and DPM */
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	li	r11,0
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	rldimi	r0,r11,32,31		/* clear EN_ATTN */
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	b	load_hids		/* Jump to shared code */
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_GLOBAL(__setup_cpu_ppc970MP)
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	/* Do nothing if not running in HV mode */
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	mfmsr	r0
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	rldicl.	r0,r0,4,63
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	beq	no_hv_mode
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	mfspr	r0,SPRN_HID0
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	li	r11,0x15		/* clear DOZE and SLEEP */
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	rldimi	r0,r11,52,6		/* set DEEPNAP, NAP and DPM */
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	li	r11,0
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	rldimi	r0,r11,32,31		/* clear EN_ATTN */
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load_hids:
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	mtspr	SPRN_HID0,r0
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	mfspr	r0,SPRN_HID0
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	mfspr	r0,SPRN_HID0
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	mfspr	r0,SPRN_HID0
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	mfspr	r0,SPRN_HID0
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	mfspr	r0,SPRN_HID0
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	mfspr	r0,SPRN_HID0
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	sync
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	isync
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	/* Try to set LPES = 01 in HID4 */
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	mfspr	r0,SPRN_HID4
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	clrldi	r0,r0,1			/* clear LPES0 */
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	ori	r0,r0,HID4_LPES1	/* set LPES1 */
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	sync
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	mtspr	SPRN_HID4,r0
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	isync
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	/* Save away cpu state */
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	LOAD_REG_ADDR(r5,cpu_state_storage)
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	/* Save HID0,1,4 and 5 */
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	mfspr	r3,SPRN_HID0
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	std	r3,CS_HID0(r5)
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	mfspr	r3,SPRN_HID1
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	std	r3,CS_HID1(r5)
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	mfspr	r4,SPRN_HID4
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	std	r4,CS_HID4(r5)
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	mfspr	r3,SPRN_HID5
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	std	r3,CS_HID5(r5)
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	/* See if we successfully set LPES1 to 1; if not we are in Apple mode */
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	andi.	r4,r4,HID4_LPES1
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	bnelr
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no_hv_mode:
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	/* Disable CPU_FTR_HVMODE and exit, since we don't have HV mode */
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	ld	r5,CPU_SPEC_FEATURES(r4)
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	LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE)
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	andc	r5,r5,r6
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	std	r5,CPU_SPEC_FEATURES(r4)
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	blr
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/* Called with no MMU context (typically MSR:IR/DR off) to
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 * restore CPU state as backed up by the previous
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 * function. This does not include cache setting
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 */
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_GLOBAL(__restore_cpu_ppc970)
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	/* Do nothing if not running in HV mode */
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	mfmsr	r0
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	rldicl.	r0,r0,4,63
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	beqlr
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	LOAD_REG_ADDR(r5,cpu_state_storage)
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	/* Before accessing memory, we make sure rm_ci is clear */
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	li	r0,0
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	mfspr	r3,SPRN_HID4
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	rldimi	r3,r0,40,23	/* clear bit 23 (rm_ci) */
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	sync
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	mtspr	SPRN_HID4,r3
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	isync
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	sync
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	/* Clear interrupt prefix */
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	li	r0,0
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	sync
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	mtspr	SPRN_HIOR,0
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	isync
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	/* Restore HID0 */
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	ld	r3,CS_HID0(r5)
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	sync
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	isync
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	mtspr	SPRN_HID0,r3
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	mfspr	r3,SPRN_HID0
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	mfspr	r3,SPRN_HID0
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	mfspr	r3,SPRN_HID0
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	mfspr	r3,SPRN_HID0
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	mfspr	r3,SPRN_HID0
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	mfspr	r3,SPRN_HID0
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	sync
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	isync
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	/* Restore HID1 */
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	ld	r3,CS_HID1(r5)
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	sync
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	isync
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	mtspr	SPRN_HID1,r3
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	mtspr	SPRN_HID1,r3
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	sync
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	isync
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	/* Restore HID4 */
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	ld	r3,CS_HID4(r5)
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	sync
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	isync
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	mtspr	SPRN_HID4,r3
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	sync
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	isync
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	/* Restore HID5 */
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	ld	r3,CS_HID5(r5)
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	sync
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	isync
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	mtspr	SPRN_HID5,r3
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	sync
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	isync
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	blr
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