/* SPDX-License-Identifier: GPL-2.0-or-later */1/*2* FPU support code, moved here from head.S so that it can be used3* by chips which use other head-whatever.S files.4*5* Copyright (C) 1995-1996 Gary Thomas ([email protected])6* Copyright (C) 1996 Cort Dougan <[email protected]>7* Copyright (C) 1996 Paul Mackerras.8* Copyright (C) 1997 Dan Malek ([email protected]).9*/1011#include <linux/export.h>12#include <asm/reg.h>13#include <asm/page.h>14#include <asm/mmu.h>15#include <asm/cputable.h>16#include <asm/cache.h>17#include <asm/thread_info.h>18#include <asm/ppc_asm.h>19#include <asm/asm-offsets.h>20#include <asm/ptrace.h>21#include <asm/asm-compat.h>22#include <asm/feature-fixups.h>2324#ifdef CONFIG_VSX25#define __REST_1FPVSR(n,c,base) \26BEGIN_FTR_SECTION \27b 2f; \28END_FTR_SECTION_IFSET(CPU_FTR_VSX); \29REST_FPR(n,base); \30b 3f; \312: REST_VSR(n,c,base); \323:3334#define __REST_32FPVSRS(n,c,base) \35BEGIN_FTR_SECTION \36b 2f; \37END_FTR_SECTION_IFSET(CPU_FTR_VSX); \38REST_32FPRS(n,base); \39b 3f; \402: REST_32VSRS(n,c,base); \413:4243#define __SAVE_32FPVSRS(n,c,base) \44BEGIN_FTR_SECTION \45b 2f; \46END_FTR_SECTION_IFSET(CPU_FTR_VSX); \47SAVE_32FPRS(n,base); \48b 3f; \492: SAVE_32VSRS(n,c,base); \503:51#else52#define __REST_1FPVSR(n,b,base) REST_FPR(n, base)53#define __REST_32FPVSRS(n,b,base) REST_32FPRS(n, base)54#define __SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base)55#endif56#define REST_1FPVSR(n,c,base) __REST_1FPVSR(n,__REG_##c,__REG_##base)57#define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base)58#define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base)5960/*61* Load state from memory into FP registers including FPSCR.62* Assumes the caller has enabled FP in the MSR.63*/64_GLOBAL(load_fp_state)65lfd fr0,FPSTATE_FPSCR(r3)66MTFSF_L(fr0)67REST_32FPVSRS(0, R4, R3)68blr69EXPORT_SYMBOL(load_fp_state)70_ASM_NOKPROBE_SYMBOL(load_fp_state); /* used by restore_math */7172/*73* Store FP state into memory, including FPSCR74* Assumes the caller has enabled FP in the MSR.75*/76_GLOBAL(store_fp_state)77SAVE_32FPVSRS(0, R4, R3)78mffs fr079stfd fr0,FPSTATE_FPSCR(r3)80REST_1FPVSR(0, R4, R3)81blr82EXPORT_SYMBOL(store_fp_state)8384/*85* This task wants to use the FPU now.86* On UP, disable FP for the task which had the FPU previously,87* and save its floating-point registers in its thread_struct.88* Load up this task's FP registers from its thread_struct,89* enable the FPU for the current task and return to the task.90* Note that on 32-bit this can only use registers that will be91* restored by fast_exception_return, i.e. r3 - r6, r10 and r11.92*/93_GLOBAL(load_up_fpu)94mfmsr r595#ifdef CONFIG_PPC_BOOK3S_6496/* interrupt doesn't set MSR[RI] and HPT can fault on current access */97ori r5,r5,MSR_FP|MSR_RI98#else99ori r5,r5,MSR_FP100#endif101#ifdef CONFIG_VSX102BEGIN_FTR_SECTION103oris r5,r5,MSR_VSX@h104END_FTR_SECTION_IFSET(CPU_FTR_VSX)105#endif106MTMSRD(r5) /* enable use of fpu now */107isync108/* enable use of FP after return */109#ifdef CONFIG_PPC32110addi r5,r2,THREAD111lwz r4,THREAD_FPEXC_MODE(r5)112ori r9,r9,MSR_FP /* enable FP for current */113or r9,r9,r4114#else115ld r4,PACACURRENT(r13)116addi r5,r4,THREAD /* Get THREAD */117lwz r4,THREAD_FPEXC_MODE(r5)118ori r12,r12,MSR_FP119or r12,r12,r4120std r12,_MSR(r1)121#ifdef CONFIG_PPC_BOOK3S_64122li r4,0123stb r4,PACASRR_VALID(r13)124#endif125#endif126li r4,1127stb r4,THREAD_LOAD_FP(r5)128addi r10,r5,THREAD_FPSTATE129lfd fr0,FPSTATE_FPSCR(r10)130MTFSF_L(fr0)131REST_32FPVSRS(0, R4, R10)132/* restore registers and return */133/* we haven't used ctr or xer or lr */134blr135_ASM_NOKPROBE_SYMBOL(load_up_fpu)136137/*138* save_fpu(tsk)139* Save the floating-point registers in its thread_struct.140* Enables the FPU for use in the kernel on return.141*/142_GLOBAL(save_fpu)143addi r3,r3,THREAD /* want THREAD of task */144PPC_LL r6,THREAD_FPSAVEAREA(r3)145PPC_LL r5,PT_REGS(r3)146PPC_LCMPI 0,r6,0147bne 2f148addi r6,r3,THREAD_FPSTATE1492: SAVE_32FPVSRS(0, R4, R6)150mffs fr0151stfd fr0,FPSTATE_FPSCR(r6)152REST_1FPVSR(0, R4, R6)153blr154155156