CoCalc -- booke_interrupts.S

GitHub Repository: torvalds/linux
Path: blob/master/arch/powerpc/kvm/booke_interrupts.S
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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 *
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 * Copyright IBM Corp. 2007
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 * Copyright 2011 Freescale Semiconductor, Inc.
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 *
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 * Authors: Hollis Blanchard <[email protected]>
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 */
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#include <asm/ppc_asm.h>
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#include <asm/kvm_asm.h>
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#include <asm/reg.h>
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#include <asm/page.h>
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#include <asm/asm-offsets.h>
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/* The host stack layout: */
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#define HOST_R1         0 /* Implied by stwu. */
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#define HOST_CALLEE_LR  4
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#define HOST_RUN        8
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/* r2 is special: it holds 'current', and it made nonvolatile in the
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 * kernel with the -ffixed-r2 gcc option. */
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#define HOST_R2         12
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#define HOST_CR         16
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#define HOST_NV_GPRS    20
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#define __HOST_NV_GPR(n)  (HOST_NV_GPRS + ((n - 14) * 4))
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#define HOST_NV_GPR(n)  __HOST_NV_GPR(__REG_##n)
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#define HOST_MIN_STACK_SIZE (HOST_NV_GPR(R31) + 4)
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#define HOST_STACK_SIZE (((HOST_MIN_STACK_SIZE + 15) / 16) * 16) /* Align. */
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#define HOST_STACK_LR   (HOST_STACK_SIZE + 4) /* In caller stack frame. */
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#define NEED_INST_MASK ((1<<BOOKE_INTERRUPT_PROGRAM) | \
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                        (1<<BOOKE_INTERRUPT_DTLB_MISS) | \
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                        (1<<BOOKE_INTERRUPT_DEBUG))
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#define NEED_DEAR_MASK ((1<<BOOKE_INTERRUPT_DATA_STORAGE) | \
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                        (1<<BOOKE_INTERRUPT_DTLB_MISS) | \
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                        (1<<BOOKE_INTERRUPT_ALIGNMENT))
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#define NEED_ESR_MASK ((1<<BOOKE_INTERRUPT_DATA_STORAGE) | \
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                       (1<<BOOKE_INTERRUPT_INST_STORAGE) | \
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                       (1<<BOOKE_INTERRUPT_PROGRAM) | \
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                       (1<<BOOKE_INTERRUPT_DTLB_MISS) | \
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                       (1<<BOOKE_INTERRUPT_ALIGNMENT))
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.macro __KVM_HANDLER ivor_nr scratch srr0
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	/* Get pointer to vcpu and record exit number. */
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	mtspr	\scratch , r4
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	mfspr   r4, SPRN_SPRG_THREAD
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	lwz     r4, THREAD_KVM_VCPU(r4)
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	stw	r3, VCPU_GPR(R3)(r4)
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	stw	r5, VCPU_GPR(R5)(r4)
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	stw	r6, VCPU_GPR(R6)(r4)
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	mfspr	r3, \scratch
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	mfctr	r5
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	stw	r3, VCPU_GPR(R4)(r4)
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	stw	r5, VCPU_CTR(r4)
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	mfspr	r3, \srr0
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	lis	r6, kvmppc_resume_host@h
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	stw	r3, VCPU_PC(r4)
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	li	r5, \ivor_nr
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	ori	r6, r6, kvmppc_resume_host@l
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	mtctr	r6
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	bctr
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.endm
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.macro KVM_HANDLER ivor_nr scratch srr0
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_GLOBAL(kvmppc_handler_\ivor_nr)
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	__KVM_HANDLER \ivor_nr \scratch \srr0
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.endm
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.macro KVM_DBG_HANDLER ivor_nr scratch srr0
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_GLOBAL(kvmppc_handler_\ivor_nr)
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	mtspr   \scratch, r4
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	mfspr	r4, SPRN_SPRG_THREAD
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	lwz	r4, THREAD_KVM_VCPU(r4)
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	stw	r3, VCPU_CRIT_SAVE(r4)
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	mfcr	r3
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	mfspr	r4, SPRN_CSRR1
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	andi.	r4, r4, MSR_PR
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	bne	1f
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	/* debug interrupt happened in enter/exit path */
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	mfspr   r4, SPRN_CSRR1
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	rlwinm  r4, r4, 0, ~MSR_DE
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	mtspr   SPRN_CSRR1, r4
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	lis	r4, 0xffff
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	ori	r4, r4, 0xffff
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	mtspr	SPRN_DBSR, r4
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	mfspr	r4, SPRN_SPRG_THREAD
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	lwz	r4, THREAD_KVM_VCPU(r4)
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	mtcr	r3
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	lwz     r3, VCPU_CRIT_SAVE(r4)
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	mfspr   r4, \scratch
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	rfci
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1:	/* debug interrupt happened in guest */
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	mtcr	r3
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	mfspr	r4, SPRN_SPRG_THREAD
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	lwz	r4, THREAD_KVM_VCPU(r4)
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	lwz     r3, VCPU_CRIT_SAVE(r4)
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	mfspr   r4, \scratch
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	__KVM_HANDLER \ivor_nr \scratch \srr0
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.endm
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.macro KVM_HANDLER_ADDR ivor_nr
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	.long	kvmppc_handler_\ivor_nr
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.endm
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.macro KVM_HANDLER_END
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	.long	kvmppc_handlers_end
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.endm
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_GLOBAL(kvmppc_handlers_start)
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KVM_HANDLER BOOKE_INTERRUPT_CRITICAL SPRN_SPRG_RSCRATCH_CRIT SPRN_CSRR0
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KVM_HANDLER BOOKE_INTERRUPT_MACHINE_CHECK  SPRN_SPRG_RSCRATCH_MC SPRN_MCSRR0
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KVM_HANDLER BOOKE_INTERRUPT_DATA_STORAGE SPRN_SPRG_RSCRATCH0 SPRN_SRR0
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KVM_HANDLER BOOKE_INTERRUPT_INST_STORAGE SPRN_SPRG_RSCRATCH0 SPRN_SRR0
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KVM_HANDLER BOOKE_INTERRUPT_EXTERNAL SPRN_SPRG_RSCRATCH0 SPRN_SRR0
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KVM_HANDLER BOOKE_INTERRUPT_ALIGNMENT SPRN_SPRG_RSCRATCH0 SPRN_SRR0
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KVM_HANDLER BOOKE_INTERRUPT_PROGRAM SPRN_SPRG_RSCRATCH0 SPRN_SRR0
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KVM_HANDLER BOOKE_INTERRUPT_FP_UNAVAIL SPRN_SPRG_RSCRATCH0 SPRN_SRR0
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KVM_HANDLER BOOKE_INTERRUPT_SYSCALL SPRN_SPRG_RSCRATCH0 SPRN_SRR0
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KVM_HANDLER BOOKE_INTERRUPT_AP_UNAVAIL SPRN_SPRG_RSCRATCH0 SPRN_SRR0
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KVM_HANDLER BOOKE_INTERRUPT_DECREMENTER SPRN_SPRG_RSCRATCH0 SPRN_SRR0
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KVM_HANDLER BOOKE_INTERRUPT_FIT SPRN_SPRG_RSCRATCH0 SPRN_SRR0
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KVM_HANDLER BOOKE_INTERRUPT_WATCHDOG SPRN_SPRG_RSCRATCH_CRIT SPRN_CSRR0
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KVM_HANDLER BOOKE_INTERRUPT_DTLB_MISS SPRN_SPRG_RSCRATCH0 SPRN_SRR0
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KVM_HANDLER BOOKE_INTERRUPT_ITLB_MISS SPRN_SPRG_RSCRATCH0 SPRN_SRR0
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KVM_DBG_HANDLER BOOKE_INTERRUPT_DEBUG SPRN_SPRG_RSCRATCH_CRIT SPRN_CSRR0
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KVM_HANDLER BOOKE_INTERRUPT_SPE_UNAVAIL SPRN_SPRG_RSCRATCH0 SPRN_SRR0
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KVM_HANDLER BOOKE_INTERRUPT_SPE_FP_DATA SPRN_SPRG_RSCRATCH0 SPRN_SRR0
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KVM_HANDLER BOOKE_INTERRUPT_SPE_FP_ROUND SPRN_SPRG_RSCRATCH0 SPRN_SRR0
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_GLOBAL(kvmppc_handlers_end)
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/* Registers:
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 *  SPRG_SCRATCH0: guest r4
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 *  r4: vcpu pointer
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 *  r5: KVM exit number
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 */
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_GLOBAL(kvmppc_resume_host)
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	mfcr	r3
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	stw	r3, VCPU_CR(r4)
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	stw	r7, VCPU_GPR(R7)(r4)
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	stw	r8, VCPU_GPR(R8)(r4)
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	stw	r9, VCPU_GPR(R9)(r4)
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	li	r6, 1
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	slw	r6, r6, r5
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#ifdef CONFIG_KVM_EXIT_TIMING
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	/* save exit time */
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1:
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	mfspr	r7, SPRN_TBRU
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	mfspr	r8, SPRN_TBRL
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	mfspr	r9, SPRN_TBRU
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	cmpw	r9, r7
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	bne	1b
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	stw	r8, VCPU_TIMING_EXIT_TBL(r4)
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	stw	r9, VCPU_TIMING_EXIT_TBU(r4)
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#endif
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	/* Save the faulting instruction and all GPRs for emulation. */
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	andi.	r7, r6, NEED_INST_MASK
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	beq	..skip_inst_copy
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	mfspr	r9, SPRN_SRR0
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	mfmsr	r8
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	ori	r7, r8, MSR_DS
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	mtmsr	r7
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	isync
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	lwz	r9, 0(r9)
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	mtmsr	r8
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	isync
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	stw	r9, VCPU_LAST_INST(r4)
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	stw	r15, VCPU_GPR(R15)(r4)
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	stw	r16, VCPU_GPR(R16)(r4)
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	stw	r17, VCPU_GPR(R17)(r4)
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	stw	r18, VCPU_GPR(R18)(r4)
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	stw	r19, VCPU_GPR(R19)(r4)
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	stw	r20, VCPU_GPR(R20)(r4)
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	stw	r21, VCPU_GPR(R21)(r4)
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	stw	r22, VCPU_GPR(R22)(r4)
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	stw	r23, VCPU_GPR(R23)(r4)
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	stw	r24, VCPU_GPR(R24)(r4)
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	stw	r25, VCPU_GPR(R25)(r4)
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	stw	r26, VCPU_GPR(R26)(r4)
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	stw	r27, VCPU_GPR(R27)(r4)
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	stw	r28, VCPU_GPR(R28)(r4)
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	stw	r29, VCPU_GPR(R29)(r4)
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	stw	r30, VCPU_GPR(R30)(r4)
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	stw	r31, VCPU_GPR(R31)(r4)
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..skip_inst_copy:
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	/* Also grab DEAR and ESR before the host can clobber them. */
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	andi.	r7, r6, NEED_DEAR_MASK
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	beq	..skip_dear
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	mfspr	r9, SPRN_DEAR
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	stw	r9, VCPU_FAULT_DEAR(r4)
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..skip_dear:
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	andi.	r7, r6, NEED_ESR_MASK
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	beq	..skip_esr
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	mfspr	r9, SPRN_ESR
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	stw	r9, VCPU_FAULT_ESR(r4)
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..skip_esr:
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	/* Save remaining volatile guest register state to vcpu. */
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	stw	r0, VCPU_GPR(R0)(r4)
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	stw	r1, VCPU_GPR(R1)(r4)
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	stw	r2, VCPU_GPR(R2)(r4)
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	stw	r10, VCPU_GPR(R10)(r4)
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	stw	r11, VCPU_GPR(R11)(r4)
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	stw	r12, VCPU_GPR(R12)(r4)
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	stw	r13, VCPU_GPR(R13)(r4)
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	stw	r14, VCPU_GPR(R14)(r4) /* We need a NV GPR below. */
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	mflr	r3
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	stw	r3, VCPU_LR(r4)
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	mfxer	r3
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	stw	r3, VCPU_XER(r4)
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	/* Restore host stack pointer and PID before IVPR, since the host
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	 * exception handlers use them. */
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	lwz	r1, VCPU_HOST_STACK(r4)
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	lwz	r3, VCPU_HOST_PID(r4)
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	mtspr	SPRN_PID, r3
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#ifdef CONFIG_PPC_85xx
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	/* we cheat and know that Linux doesn't use PID1 which is always 0 */
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	lis	r3, 0
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	mtspr	SPRN_PID1, r3
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#endif
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	/* Restore host IVPR before re-enabling interrupts. We cheat and know
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	 * that Linux IVPR is always 0xc0000000. */
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	lis	r3, 0xc000
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	mtspr	SPRN_IVPR, r3
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	/* Switch to kernel stack and jump to handler. */
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	LOAD_REG_ADDR(r3, kvmppc_handle_exit)
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	mtctr	r3
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	mr	r3, r4
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	lwz	r2, HOST_R2(r1)
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	mr	r14, r4 /* Save vcpu pointer. */
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	bctrl	/* kvmppc_handle_exit() */
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	/* Restore vcpu pointer and the nonvolatiles we used. */
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	mr	r4, r14
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	lwz	r14, VCPU_GPR(R14)(r4)
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	/* Sometimes instruction emulation must restore complete GPR state. */
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	andi.	r5, r3, RESUME_FLAG_NV
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	beq	..skip_nv_load
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	lwz	r15, VCPU_GPR(R15)(r4)
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	lwz	r16, VCPU_GPR(R16)(r4)
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	lwz	r17, VCPU_GPR(R17)(r4)
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	lwz	r18, VCPU_GPR(R18)(r4)
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	lwz	r19, VCPU_GPR(R19)(r4)
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	lwz	r20, VCPU_GPR(R20)(r4)
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	lwz	r21, VCPU_GPR(R21)(r4)
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	lwz	r22, VCPU_GPR(R22)(r4)
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	lwz	r23, VCPU_GPR(R23)(r4)
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	lwz	r24, VCPU_GPR(R24)(r4)
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	lwz	r25, VCPU_GPR(R25)(r4)
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	lwz	r26, VCPU_GPR(R26)(r4)
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	lwz	r27, VCPU_GPR(R27)(r4)
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	lwz	r28, VCPU_GPR(R28)(r4)
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	lwz	r29, VCPU_GPR(R29)(r4)
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	lwz	r30, VCPU_GPR(R30)(r4)
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	lwz	r31, VCPU_GPR(R31)(r4)
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..skip_nv_load:
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	/* Should we return to the guest? */
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	andi.	r5, r3, RESUME_FLAG_HOST
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	beq	lightweight_exit
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	srawi	r3, r3, 2 /* Shift -ERR back down. */
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heavyweight_exit:
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	/* Not returning to guest. */
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#ifdef CONFIG_SPE
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	/* save guest SPEFSCR and load host SPEFSCR */
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	mfspr	r9, SPRN_SPEFSCR
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	stw	r9, VCPU_SPEFSCR(r4)
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	lwz	r9, VCPU_HOST_SPEFSCR(r4)
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	mtspr	SPRN_SPEFSCR, r9
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#endif
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	/* We already saved guest volatile register state; now save the
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	 * non-volatiles. */
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	stw	r15, VCPU_GPR(R15)(r4)
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	stw	r16, VCPU_GPR(R16)(r4)
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	stw	r17, VCPU_GPR(R17)(r4)
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	stw	r18, VCPU_GPR(R18)(r4)
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	stw	r19, VCPU_GPR(R19)(r4)
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	stw	r20, VCPU_GPR(R20)(r4)
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	stw	r21, VCPU_GPR(R21)(r4)
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	stw	r22, VCPU_GPR(R22)(r4)
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	stw	r23, VCPU_GPR(R23)(r4)
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	stw	r24, VCPU_GPR(R24)(r4)
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	stw	r25, VCPU_GPR(R25)(r4)
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	stw	r26, VCPU_GPR(R26)(r4)
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	stw	r27, VCPU_GPR(R27)(r4)
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	stw	r28, VCPU_GPR(R28)(r4)
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	stw	r29, VCPU_GPR(R29)(r4)
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	stw	r30, VCPU_GPR(R30)(r4)
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	stw	r31, VCPU_GPR(R31)(r4)
308

309
	/* Load host non-volatile register state from host stack. */
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	lwz	r14, HOST_NV_GPR(R14)(r1)
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	lwz	r15, HOST_NV_GPR(R15)(r1)
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	lwz	r16, HOST_NV_GPR(R16)(r1)
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	lwz	r17, HOST_NV_GPR(R17)(r1)
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	lwz	r18, HOST_NV_GPR(R18)(r1)
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	lwz	r19, HOST_NV_GPR(R19)(r1)
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	lwz	r20, HOST_NV_GPR(R20)(r1)
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	lwz	r21, HOST_NV_GPR(R21)(r1)
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	lwz	r22, HOST_NV_GPR(R22)(r1)
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	lwz	r23, HOST_NV_GPR(R23)(r1)
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	lwz	r24, HOST_NV_GPR(R24)(r1)
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	lwz	r25, HOST_NV_GPR(R25)(r1)
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	lwz	r26, HOST_NV_GPR(R26)(r1)
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	lwz	r27, HOST_NV_GPR(R27)(r1)
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	lwz	r28, HOST_NV_GPR(R28)(r1)
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	lwz	r29, HOST_NV_GPR(R29)(r1)
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	lwz	r30, HOST_NV_GPR(R30)(r1)
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	lwz	r31, HOST_NV_GPR(R31)(r1)
328

329
	/* Return to kvm_vcpu_run(). */
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	lwz	r4, HOST_STACK_LR(r1)
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	lwz	r5, HOST_CR(r1)
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	addi	r1, r1, HOST_STACK_SIZE
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	mtlr	r4
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	mtcr	r5
335
	/* r3 still contains the return code from kvmppc_handle_exit(). */
336
	blr
337

338

339
/* Registers:
340
 *  r3: vcpu pointer
341
 */
342
_GLOBAL(__kvmppc_vcpu_run)
343
	stwu	r1, -HOST_STACK_SIZE(r1)
344
	stw	r1, VCPU_HOST_STACK(r3)	/* Save stack pointer to vcpu. */
345

346
	/* Save host state to stack. */
347
	mr	r4, r3
348
	mflr	r3
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	stw	r3, HOST_STACK_LR(r1)
350
	mfcr	r5
351
	stw	r5, HOST_CR(r1)
352

353
	/* Save host non-volatile register state to stack. */
354
	stw	r14, HOST_NV_GPR(R14)(r1)
355
	stw	r15, HOST_NV_GPR(R15)(r1)
356
	stw	r16, HOST_NV_GPR(R16)(r1)
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	stw	r17, HOST_NV_GPR(R17)(r1)
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	stw	r18, HOST_NV_GPR(R18)(r1)
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	stw	r19, HOST_NV_GPR(R19)(r1)
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	stw	r20, HOST_NV_GPR(R20)(r1)
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	stw	r21, HOST_NV_GPR(R21)(r1)
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	stw	r22, HOST_NV_GPR(R22)(r1)
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	stw	r23, HOST_NV_GPR(R23)(r1)
364
	stw	r24, HOST_NV_GPR(R24)(r1)
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	stw	r25, HOST_NV_GPR(R25)(r1)
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	stw	r26, HOST_NV_GPR(R26)(r1)
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	stw	r27, HOST_NV_GPR(R27)(r1)
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	stw	r28, HOST_NV_GPR(R28)(r1)
369
	stw	r29, HOST_NV_GPR(R29)(r1)
370
	stw	r30, HOST_NV_GPR(R30)(r1)
371
	stw	r31, HOST_NV_GPR(R31)(r1)
372

373
	/* Load guest non-volatiles. */
374
	lwz	r14, VCPU_GPR(R14)(r4)
375
	lwz	r15, VCPU_GPR(R15)(r4)
376
	lwz	r16, VCPU_GPR(R16)(r4)
377
	lwz	r17, VCPU_GPR(R17)(r4)
378
	lwz	r18, VCPU_GPR(R18)(r4)
379
	lwz	r19, VCPU_GPR(R19)(r4)
380
	lwz	r20, VCPU_GPR(R20)(r4)
381
	lwz	r21, VCPU_GPR(R21)(r4)
382
	lwz	r22, VCPU_GPR(R22)(r4)
383
	lwz	r23, VCPU_GPR(R23)(r4)
384
	lwz	r24, VCPU_GPR(R24)(r4)
385
	lwz	r25, VCPU_GPR(R25)(r4)
386
	lwz	r26, VCPU_GPR(R26)(r4)
387
	lwz	r27, VCPU_GPR(R27)(r4)
388
	lwz	r28, VCPU_GPR(R28)(r4)
389
	lwz	r29, VCPU_GPR(R29)(r4)
390
	lwz	r30, VCPU_GPR(R30)(r4)
391
	lwz	r31, VCPU_GPR(R31)(r4)
392

393
#ifdef CONFIG_SPE
394
	/* save host SPEFSCR and load guest SPEFSCR */
395
	mfspr	r3, SPRN_SPEFSCR
396
	stw	r3, VCPU_HOST_SPEFSCR(r4)
397
	lwz	r3, VCPU_SPEFSCR(r4)
398
	mtspr	SPRN_SPEFSCR, r3
399
#endif
400

401
lightweight_exit:
402
	stw	r2, HOST_R2(r1)
403

404
	mfspr	r3, SPRN_PID
405
	stw	r3, VCPU_HOST_PID(r4)
406
	lwz	r3, VCPU_SHADOW_PID(r4)
407
	mtspr	SPRN_PID, r3
408

409
#ifdef CONFIG_PPC_85xx
410
	lwz	r3, VCPU_SHADOW_PID1(r4)
411
	mtspr	SPRN_PID1, r3
412
#endif
413

414
	/* Load some guest volatiles. */
415
	lwz	r0, VCPU_GPR(R0)(r4)
416
	lwz	r2, VCPU_GPR(R2)(r4)
417
	lwz	r9, VCPU_GPR(R9)(r4)
418
	lwz	r10, VCPU_GPR(R10)(r4)
419
	lwz	r11, VCPU_GPR(R11)(r4)
420
	lwz	r12, VCPU_GPR(R12)(r4)
421
	lwz	r13, VCPU_GPR(R13)(r4)
422
	lwz	r3, VCPU_LR(r4)
423
	mtlr	r3
424
	lwz	r3, VCPU_XER(r4)
425
	mtxer	r3
426

427
	/* Switch the IVPR. XXX If we take a TLB miss after this we're screwed,
428
	 * so how do we make sure vcpu won't fault? */
429
	lis	r8, kvmppc_booke_handlers@ha
430
	lwz	r8, kvmppc_booke_handlers@l(r8)
431
	mtspr	SPRN_IVPR, r8
432

433
	lwz	r5, VCPU_SHARED(r4)
434

435
	/* Can't switch the stack pointer until after IVPR is switched,
436
	 * because host interrupt handlers would get confused. */
437
	lwz	r1, VCPU_GPR(R1)(r4)
438

439
	/*
440
	 * Host interrupt handlers may have clobbered these
441
	 * guest-readable SPRGs, or the guest kernel may have
442
	 * written directly to the shared area, so we
443
	 * need to reload them here with the guest's values.
444
	 */
445
	PPC_LD(r3, VCPU_SHARED_SPRG4, r5)
446
	mtspr	SPRN_SPRG4W, r3
447
	PPC_LD(r3, VCPU_SHARED_SPRG5, r5)
448
	mtspr	SPRN_SPRG5W, r3
449
	PPC_LD(r3, VCPU_SHARED_SPRG6, r5)
450
	mtspr	SPRN_SPRG6W, r3
451
	PPC_LD(r3, VCPU_SHARED_SPRG7, r5)
452
	mtspr	SPRN_SPRG7W, r3
453

454
#ifdef CONFIG_KVM_EXIT_TIMING
455
	/* save enter time */
456
1:
457
	mfspr	r6, SPRN_TBRU
458
	mfspr	r7, SPRN_TBRL
459
	mfspr	r8, SPRN_TBRU
460
	cmpw	r8, r6
461
	bne	1b
462
	stw	r7, VCPU_TIMING_LAST_ENTER_TBL(r4)
463
	stw	r8, VCPU_TIMING_LAST_ENTER_TBU(r4)
464
#endif
465

466
	/* Finish loading guest volatiles and jump to guest. */
467
	lwz	r3, VCPU_CTR(r4)
468
	lwz	r5, VCPU_CR(r4)
469
	lwz	r6, VCPU_PC(r4)
470
	lwz	r7, VCPU_SHADOW_MSR(r4)
471
	mtctr	r3
472
	mtcr	r5
473
	mtsrr0	r6
474
	mtsrr1	r7
475
	lwz	r5, VCPU_GPR(R5)(r4)
476
	lwz	r6, VCPU_GPR(R6)(r4)
477
	lwz	r7, VCPU_GPR(R7)(r4)
478
	lwz	r8, VCPU_GPR(R8)(r4)
479

480
	/* Clear any debug events which occurred since we disabled MSR[DE].
481
	 * XXX This gives us a 3-instruction window in which a breakpoint
482
	 * intended for guest context could fire in the host instead. */
483
	lis	r3, 0xffff
484
	ori	r3, r3, 0xffff
485
	mtspr	SPRN_DBSR, r3
486

487
	lwz	r3, VCPU_GPR(R3)(r4)
488
	lwz	r4, VCPU_GPR(R4)(r4)
489
	rfi
490

491
	.data
492
	.align	4
493
	.globl	kvmppc_booke_handler_addr
494
kvmppc_booke_handler_addr:
495
KVM_HANDLER_ADDR BOOKE_INTERRUPT_CRITICAL
496
KVM_HANDLER_ADDR BOOKE_INTERRUPT_MACHINE_CHECK
497
KVM_HANDLER_ADDR BOOKE_INTERRUPT_DATA_STORAGE
498
KVM_HANDLER_ADDR BOOKE_INTERRUPT_INST_STORAGE
499
KVM_HANDLER_ADDR BOOKE_INTERRUPT_EXTERNAL
500
KVM_HANDLER_ADDR BOOKE_INTERRUPT_ALIGNMENT
501
KVM_HANDLER_ADDR BOOKE_INTERRUPT_PROGRAM
502
KVM_HANDLER_ADDR BOOKE_INTERRUPT_FP_UNAVAIL
503
KVM_HANDLER_ADDR BOOKE_INTERRUPT_SYSCALL
504
KVM_HANDLER_ADDR BOOKE_INTERRUPT_AP_UNAVAIL
505
KVM_HANDLER_ADDR BOOKE_INTERRUPT_DECREMENTER
506
KVM_HANDLER_ADDR BOOKE_INTERRUPT_FIT
507
KVM_HANDLER_ADDR BOOKE_INTERRUPT_WATCHDOG
508
KVM_HANDLER_ADDR BOOKE_INTERRUPT_DTLB_MISS
509
KVM_HANDLER_ADDR BOOKE_INTERRUPT_ITLB_MISS
510
KVM_HANDLER_ADDR BOOKE_INTERRUPT_DEBUG
511
KVM_HANDLER_ADDR BOOKE_INTERRUPT_SPE_UNAVAIL
512
KVM_HANDLER_ADDR BOOKE_INTERRUPT_SPE_FP_DATA
513
KVM_HANDLER_ADDR BOOKE_INTERRUPT_SPE_FP_ROUND
514
KVM_HANDLER_END /*Always keep this in end*/
515

516
#ifdef CONFIG_SPE
517
_GLOBAL(kvmppc_save_guest_spe)
518
	cmpi	0,r3,0
519
	beqlr-
520
	SAVE_32EVRS(0, r4, r3, VCPU_EVR)
521
	evxor   evr6, evr6, evr6
522
	evmwumiaa evr6, evr6, evr6
523
	li	r4,VCPU_ACC
524
	evstddx evr6, r4, r3		/* save acc */
525
	blr
526

527
_GLOBAL(kvmppc_load_guest_spe)
528
	cmpi	0,r3,0
529
	beqlr-
530
	li      r4,VCPU_ACC
531
	evlddx  evr6,r4,r3
532
	evmra   evr6,evr6		/* load acc */
533
	REST_32EVRS(0, r4, r3, VCPU_EVR)
534
	blr
535
#endif
536

537
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