Path: blob/master/arch/powerpc/mm/book3s64/radix_hugetlbpage.c
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// SPDX-License-Identifier: GPL-2.01#include <linux/mm.h>2#include <linux/hugetlb.h>3#include <linux/security.h>4#include <asm/cacheflush.h>5#include <asm/machdep.h>6#include <asm/mman.h>7#include <asm/tlb.h>89void radix__flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr)10{11int psize;12struct hstate *hstate = hstate_file(vma->vm_file);1314psize = hstate_get_psize(hstate);15radix__flush_tlb_page_psize(vma->vm_mm, vmaddr, psize);16}1718void radix__local_flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr)19{20int psize;21struct hstate *hstate = hstate_file(vma->vm_file);2223psize = hstate_get_psize(hstate);24radix__local_flush_tlb_page_psize(vma->vm_mm, vmaddr, psize);25}2627void radix__flush_hugetlb_tlb_range(struct vm_area_struct *vma, unsigned long start,28unsigned long end)29{30int psize;31struct hstate *hstate = hstate_file(vma->vm_file);3233psize = hstate_get_psize(hstate);34/*35* Flush PWC even if we get PUD_SIZE hugetlb invalidate to keep this simpler.36*/37if (end - start >= PUD_SIZE)38radix__flush_tlb_pwc_range_psize(vma->vm_mm, start, end, psize);39else40radix__flush_tlb_range_psize(vma->vm_mm, start, end, psize);41mmu_notifier_arch_invalidate_secondary_tlbs(vma->vm_mm, start, end);42}4344void radix__huge_ptep_modify_prot_commit(struct vm_area_struct *vma,45unsigned long addr, pte_t *ptep,46pte_t old_pte, pte_t pte)47{48struct mm_struct *mm = vma->vm_mm;49unsigned long psize = huge_page_size(hstate_vma(vma));5051/*52* POWER9 NMMU must flush the TLB after clearing the PTE before53* installing a PTE with more relaxed access permissions, see54* radix__ptep_set_access_flags.55*/56if (!cpu_has_feature(CPU_FTR_ARCH_31) &&57is_pte_rw_upgrade(pte_val(old_pte), pte_val(pte)) &&58atomic_read(&mm->context.copros) > 0)59radix__flush_hugetlb_page(vma, addr);6061set_huge_pte_at(vma->vm_mm, addr, ptep, pte, psize);62}636465