CoCalc -- suspend-asm.S

GitHub Repository: torvalds/linux
Path: blob/master/arch/powerpc/platforms/83xx/suspend-asm.S
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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 * Enter and leave deep sleep state on MPC83xx
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 *
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 * Copyright (c) 2006-2008 Freescale Semiconductor, Inc.
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 * Author: Scott Wood <[email protected]>
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 */
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#include <asm/page.h>
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#include <asm/ppc_asm.h>
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#include <asm/reg.h>
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#include <asm/asm-offsets.h>
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#define SS_MEMSAVE	0x00 /* First 8 bytes of RAM */
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#define SS_HID		0x08 /* 3 HIDs */
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#define SS_IABR		0x14 /* 2 IABRs */
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#define SS_IBCR		0x1c
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#define SS_DABR		0x20 /* 2 DABRs */
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#define SS_DBCR		0x28
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#define SS_SP		0x2c
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#define SS_SR		0x30 /* 16 segment registers */
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#define SS_R2		0x70
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#define SS_MSR		0x74
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#define SS_SDR1		0x78
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#define SS_LR		0x7c
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#define SS_SPRG		0x80 /* 8 SPRGs */
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#define SS_DBAT		0xa0 /* 8 DBATs */
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#define SS_IBAT		0xe0 /* 8 IBATs */
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#define SS_TB		0x120
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#define SS_CR		0x128
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#define SS_GPREG	0x12c /* r12-r31 */
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#define STATE_SAVE_SIZE 0x17c
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	.section .data
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	.align	5
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mpc83xx_sleep_save_area:
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	.space	STATE_SAVE_SIZE
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immrbase:
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	.long	0
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	.section .text
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	.align	5
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	/* r3 = physical address of IMMR */
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_GLOBAL(mpc83xx_enter_deep_sleep)
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	lis	r4, immrbase@ha
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	stw	r3, immrbase@l(r4)
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	/* The first 2 words of memory are used to communicate with the
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	 * bootloader, to tell it how to resume.
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	 *
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	 * The first word is the magic number 0xf5153ae5, and the second
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	 * is the pointer to mpc83xx_deep_resume.
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	 *
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	 * The original content of these two words is saved in SS_MEMSAVE.
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	 */
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	lis	r3, mpc83xx_sleep_save_area@h
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	ori	r3, r3, mpc83xx_sleep_save_area@l
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	lis	r4, KERNELBASE@h
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	lwz	r5, 0(r4)
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	lwz	r6, 4(r4)
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	stw	r5, SS_MEMSAVE+0(r3)
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	stw	r6, SS_MEMSAVE+4(r3)
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	mfspr	r5, SPRN_HID0
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	mfspr	r6, SPRN_HID1
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	/* FIXME: Should this use SPRN_HID2_G2_LE? */
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	mfspr	r7, SPRN_HID2_750FX
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	stw	r5, SS_HID+0(r3)
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	stw	r6, SS_HID+4(r3)
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	stw	r7, SS_HID+8(r3)
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	mfspr	r4, SPRN_IABR
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	mfspr	r5, SPRN_IABR2
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	mfspr	r6, SPRN_IBCR
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	mfspr	r7, SPRN_DABR
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	mfspr	r8, SPRN_DABR2
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	mfspr	r9, SPRN_DBCR
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	stw	r4, SS_IABR+0(r3)
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	stw	r5, SS_IABR+4(r3)
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	stw	r6, SS_IBCR(r3)
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	stw	r7, SS_DABR+0(r3)
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	stw	r8, SS_DABR+4(r3)
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	stw	r9, SS_DBCR(r3)
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	mfspr	r4, SPRN_SPRG0
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	mfspr	r5, SPRN_SPRG1
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	mfspr	r6, SPRN_SPRG2
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	mfspr	r7, SPRN_SPRG3
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	mfsdr1	r8
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	stw	r4, SS_SPRG+0(r3)
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	stw	r5, SS_SPRG+4(r3)
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	stw	r6, SS_SPRG+8(r3)
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	stw	r7, SS_SPRG+12(r3)
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	stw	r8, SS_SDR1(r3)
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	mfspr	r4, SPRN_SPRG4
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	mfspr	r5, SPRN_SPRG5
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	mfspr	r6, SPRN_SPRG6
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	mfspr	r7, SPRN_SPRG7
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	stw	r4, SS_SPRG+16(r3)
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	stw	r5, SS_SPRG+20(r3)
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	stw	r6, SS_SPRG+24(r3)
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	stw	r7, SS_SPRG+28(r3)
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	mfspr	r4, SPRN_DBAT0U
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	mfspr	r5, SPRN_DBAT0L
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	mfspr	r6, SPRN_DBAT1U
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	mfspr	r7, SPRN_DBAT1L
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	stw	r4, SS_DBAT+0x00(r3)
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	stw	r5, SS_DBAT+0x04(r3)
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	stw	r6, SS_DBAT+0x08(r3)
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	stw	r7, SS_DBAT+0x0c(r3)
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	mfspr	r4, SPRN_DBAT2U
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	mfspr	r5, SPRN_DBAT2L
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	mfspr	r6, SPRN_DBAT3U
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	mfspr	r7, SPRN_DBAT3L
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	stw	r4, SS_DBAT+0x10(r3)
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	stw	r5, SS_DBAT+0x14(r3)
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	stw	r6, SS_DBAT+0x18(r3)
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	stw	r7, SS_DBAT+0x1c(r3)
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	mfspr	r4, SPRN_DBAT4U
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	mfspr	r5, SPRN_DBAT4L
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	mfspr	r6, SPRN_DBAT5U
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	mfspr	r7, SPRN_DBAT5L
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	stw	r4, SS_DBAT+0x20(r3)
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	stw	r5, SS_DBAT+0x24(r3)
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	stw	r6, SS_DBAT+0x28(r3)
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	stw	r7, SS_DBAT+0x2c(r3)
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	mfspr	r4, SPRN_DBAT6U
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	mfspr	r5, SPRN_DBAT6L
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	mfspr	r6, SPRN_DBAT7U
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	mfspr	r7, SPRN_DBAT7L
148

149
	stw	r4, SS_DBAT+0x30(r3)
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	stw	r5, SS_DBAT+0x34(r3)
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	stw	r6, SS_DBAT+0x38(r3)
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	stw	r7, SS_DBAT+0x3c(r3)
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	mfspr	r4, SPRN_IBAT0U
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	mfspr	r5, SPRN_IBAT0L
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	mfspr	r6, SPRN_IBAT1U
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	mfspr	r7, SPRN_IBAT1L
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	stw	r4, SS_IBAT+0x00(r3)
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	stw	r5, SS_IBAT+0x04(r3)
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	stw	r6, SS_IBAT+0x08(r3)
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	stw	r7, SS_IBAT+0x0c(r3)
163

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	mfspr	r4, SPRN_IBAT2U
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	mfspr	r5, SPRN_IBAT2L
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	mfspr	r6, SPRN_IBAT3U
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	mfspr	r7, SPRN_IBAT3L
168

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	stw	r4, SS_IBAT+0x10(r3)
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	stw	r5, SS_IBAT+0x14(r3)
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	stw	r6, SS_IBAT+0x18(r3)
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	stw	r7, SS_IBAT+0x1c(r3)
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	mfspr	r4, SPRN_IBAT4U
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	mfspr	r5, SPRN_IBAT4L
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	mfspr	r6, SPRN_IBAT5U
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	mfspr	r7, SPRN_IBAT5L
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	stw	r4, SS_IBAT+0x20(r3)
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	stw	r5, SS_IBAT+0x24(r3)
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	stw	r6, SS_IBAT+0x28(r3)
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	stw	r7, SS_IBAT+0x2c(r3)
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	mfspr	r4, SPRN_IBAT6U
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	mfspr	r5, SPRN_IBAT6L
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	mfspr	r6, SPRN_IBAT7U
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	mfspr	r7, SPRN_IBAT7L
188

189
	stw	r4, SS_IBAT+0x30(r3)
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	stw	r5, SS_IBAT+0x34(r3)
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	stw	r6, SS_IBAT+0x38(r3)
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	stw	r7, SS_IBAT+0x3c(r3)
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	mfmsr	r4
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	mflr	r5
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	mfcr	r6
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	stw	r4, SS_MSR(r3)
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	stw	r5, SS_LR(r3)
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	stw	r6, SS_CR(r3)
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	stw	r1, SS_SP(r3)
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	stw	r2, SS_R2(r3)
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1:	mftbu	r4
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	mftb	r5
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	mftbu	r6
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	cmpw	r4, r6
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	bne	1b
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	stw	r4, SS_TB+0(r3)
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	stw	r5, SS_TB+4(r3)
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	stmw	r12, SS_GPREG(r3)
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	li	r4, 0
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	addi	r6, r3, SS_SR-4
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1:	mfsrin	r5, r4
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	stwu	r5, 4(r6)
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	addis	r4, r4, 0x1000
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	cmpwi	r4, 0
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	bne	1b
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	/* Disable machine checks and critical exceptions */
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	mfmsr	r4
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	rlwinm	r4, r4, 0, ~MSR_CE
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	rlwinm	r4, r4, 0, ~MSR_ME
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	mtmsr	r4
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	isync
229

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#define TMP_VIRT_IMMR		0xf0000000
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#define DEFAULT_IMMR_VALUE	0xff400000
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#define IMMRBAR_BASE		0x0000
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	lis	r4, immrbase@ha
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	lwz	r4, immrbase@l(r4)
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	/* Use DBAT0 to address the current IMMR space */
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	ori	r4, r4, 0x002a
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	mtspr	SPRN_DBAT0L, r4
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	lis	r8, TMP_VIRT_IMMR@h
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	ori	r4, r8, 0x001e	/* 1 MByte accessible from Kernel Space only */
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	mtspr	SPRN_DBAT0U, r4
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	isync
245

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	/* Use DBAT1 to address the original IMMR space */
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	lis	r4, DEFAULT_IMMR_VALUE@h
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	ori	r4, r4, 0x002a
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	mtspr	SPRN_DBAT1L, r4
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	lis	r9, (TMP_VIRT_IMMR + 0x01000000)@h
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	ori	r4, r9, 0x001e	/* 1 MByte accessible from Kernel Space only */
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	mtspr	SPRN_DBAT1U, r4
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	isync
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	/* Use DBAT2 to address the beginning of RAM.  This isn't done
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	 * using the normal virtual mapping, because with page debugging
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	 * enabled it will be read-only.
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	 */
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	li	r4, 0x0002
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	mtspr	SPRN_DBAT2L, r4
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	lis	r4, KERNELBASE@h
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	ori	r4, r4, 0x001e	/* 1 MByte accessible from Kernel Space only */
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	mtspr	SPRN_DBAT2U, r4
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	isync
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	/* Flush the cache with our BAT, as there will be TLB misses
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	 * otherwise if page debugging is enabled, and these misses
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	 * will disturb the PLRU algorithm.
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	 */
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	bl	__flush_disable_L1
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	/* Keep the i-cache enabled, so the hack below for low-boot
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	 * flash will work.
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	 */
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	mfspr	r3, SPRN_HID0
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	ori	r3, r3, HID0_ICE
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	mtspr	SPRN_HID0, r3
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	isync
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	lis	r6, 0xf515
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	ori	r6, r6, 0x3ae5
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	lis	r7, mpc83xx_deep_resume@h
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	ori	r7, r7, mpc83xx_deep_resume@l
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	tophys(r7, r7)
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	lis	r5, KERNELBASE@h
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	stw	r6, 0(r5)
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	stw	r7, 4(r5)
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294
	/* Reset BARs */
295

296
	li	r4, 0
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	stw	r4, 0x0024(r8)
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	stw	r4, 0x002c(r8)
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	stw	r4, 0x0034(r8)
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	stw	r4, 0x003c(r8)
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	stw	r4, 0x0064(r8)
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	stw	r4, 0x006c(r8)
303

304
	/* Rev 1 of the 8313 has problems with wakeup events that are
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	 * pending during the transition to deep sleep state (such as if
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	 * the PCI host sets the state to D3 and then D0 in rapid
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	 * succession).  This check shrinks the race window somewhat.
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	 *
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	 * See erratum PCI23, though the problem is not limited
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	 * to PCI.
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	 */
312

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	lwz	r3, 0x0b04(r8)
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	andi.	r3, r3, 1
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	bne-	mpc83xx_deep_resume
316

317
	/* Move IMMR back to the default location, following the
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	 * procedure specified in the MPC8313 manual.
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	 */
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	lwz	r4, IMMRBAR_BASE(r8)
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	isync
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	lis	r4, DEFAULT_IMMR_VALUE@h
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	stw	r4, IMMRBAR_BASE(r8)
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	lis	r4, KERNELBASE@h
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	lwz	r4, 0(r4)
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	isync
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	lwz	r4, IMMRBAR_BASE(r9)
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	mr	r8, r9
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	isync
330

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	/* Check the Reset Configuration Word to see whether flash needs
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	 * to be mapped at a low address or a high address.
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	 */
334

335
	lwz	r4, 0x0904(r8)
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	andis.	r4, r4, 0x0400
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	li	r4, 0
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	beq	boot_low
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	lis	r4, 0xff80
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boot_low:
341
	stw	r4, 0x0020(r8)
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	lis	r7, 0x8000
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	ori	r7, r7, 0x0016
344

345
	mfspr	r5, SPRN_HID0
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	rlwinm	r5, r5, 0, ~(HID0_DOZE | HID0_NAP)
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	oris	r5, r5, HID0_SLEEP@h
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	mtspr	SPRN_HID0, r5
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	isync
350

351
	mfmsr	r5
352
	oris	r5, r5, MSR_POW@h
353

354
	/* Enable the flash mapping at the appropriate address.  This
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	 * mapping will override the RAM mapping if booting low, so there's
356
	 * no need to disable the latter.  This must be done inside the same
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	 * cache line as setting MSR_POW, so that no instruction fetches
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	 * from RAM happen after the flash mapping is turned on.
359
	 */
360

361
	.align	5
362
	stw	r7, 0x0024(r8)
363
	sync
364
	isync
365
	mtmsr	r5
366
	isync
367
1:	b	1b
368

369
mpc83xx_deep_resume:
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	lis	r4, 1f@h
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	ori	r4, r4, 1f@l
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	tophys(r4, r4)
373
	mtsrr0	r4
374

375
	mfmsr	r4
376
	rlwinm	r4, r4, 0, ~(MSR_IR | MSR_DR)
377
	mtsrr1	r4
378

379
	rfi
380

381
1:	tlbia
382
	bl	__inval_enable_L1
383

384
	lis	r3, mpc83xx_sleep_save_area@h
385
	ori	r3, r3, mpc83xx_sleep_save_area@l
386
	tophys(r3, r3)
387

388
	lwz	r5, SS_MEMSAVE+0(r3)
389
	lwz	r6, SS_MEMSAVE+4(r3)
390

391
	stw	r5, 0(0)
392
	stw	r6, 4(0)
393

394
	lwz	r5, SS_HID+0(r3)
395
	lwz	r6, SS_HID+4(r3)
396
	lwz	r7, SS_HID+8(r3)
397

398
	mtspr	SPRN_HID0, r5
399
	mtspr	SPRN_HID1, r6
400
	/* FIXME: Should this use SPRN_HID2_G2_LE? */
401
	mtspr	SPRN_HID2_750FX, r7
402

403
	lwz	r4, SS_IABR+0(r3)
404
	lwz	r5, SS_IABR+4(r3)
405
	lwz	r6, SS_IBCR(r3)
406
	lwz	r7, SS_DABR+0(r3)
407
	lwz	r8, SS_DABR+4(r3)
408
	lwz	r9, SS_DBCR(r3)
409

410
	mtspr	SPRN_IABR, r4
411
	mtspr	SPRN_IABR2, r5
412
	mtspr	SPRN_IBCR, r6
413
	mtspr	SPRN_DABR, r7
414
	mtspr	SPRN_DABR2, r8
415
	mtspr	SPRN_DBCR, r9
416

417
	li	r4, 0
418
	addi	r6, r3, SS_SR-4
419
1:	lwzu	r5, 4(r6)
420
	mtsrin	r5, r4
421
	addis	r4, r4, 0x1000
422
	cmpwi	r4, 0
423
	bne	1b
424

425
	lwz	r4, SS_DBAT+0x00(r3)
426
	lwz	r5, SS_DBAT+0x04(r3)
427
	lwz	r6, SS_DBAT+0x08(r3)
428
	lwz	r7, SS_DBAT+0x0c(r3)
429

430
	mtspr	SPRN_DBAT0U, r4
431
	mtspr	SPRN_DBAT0L, r5
432
	mtspr	SPRN_DBAT1U, r6
433
	mtspr	SPRN_DBAT1L, r7
434

435
	lwz	r4, SS_DBAT+0x10(r3)
436
	lwz	r5, SS_DBAT+0x14(r3)
437
	lwz	r6, SS_DBAT+0x18(r3)
438
	lwz	r7, SS_DBAT+0x1c(r3)
439

440
	mtspr	SPRN_DBAT2U, r4
441
	mtspr	SPRN_DBAT2L, r5
442
	mtspr	SPRN_DBAT3U, r6
443
	mtspr	SPRN_DBAT3L, r7
444

445
	lwz	r4, SS_DBAT+0x20(r3)
446
	lwz	r5, SS_DBAT+0x24(r3)
447
	lwz	r6, SS_DBAT+0x28(r3)
448
	lwz	r7, SS_DBAT+0x2c(r3)
449

450
	mtspr	SPRN_DBAT4U, r4
451
	mtspr	SPRN_DBAT4L, r5
452
	mtspr	SPRN_DBAT5U, r6
453
	mtspr	SPRN_DBAT5L, r7
454

455
	lwz	r4, SS_DBAT+0x30(r3)
456
	lwz	r5, SS_DBAT+0x34(r3)
457
	lwz	r6, SS_DBAT+0x38(r3)
458
	lwz	r7, SS_DBAT+0x3c(r3)
459

460
	mtspr	SPRN_DBAT6U, r4
461
	mtspr	SPRN_DBAT6L, r5
462
	mtspr	SPRN_DBAT7U, r6
463
	mtspr	SPRN_DBAT7L, r7
464

465
	lwz	r4, SS_IBAT+0x00(r3)
466
	lwz	r5, SS_IBAT+0x04(r3)
467
	lwz	r6, SS_IBAT+0x08(r3)
468
	lwz	r7, SS_IBAT+0x0c(r3)
469

470
	mtspr	SPRN_IBAT0U, r4
471
	mtspr	SPRN_IBAT0L, r5
472
	mtspr	SPRN_IBAT1U, r6
473
	mtspr	SPRN_IBAT1L, r7
474

475
	lwz	r4, SS_IBAT+0x10(r3)
476
	lwz	r5, SS_IBAT+0x14(r3)
477
	lwz	r6, SS_IBAT+0x18(r3)
478
	lwz	r7, SS_IBAT+0x1c(r3)
479

480
	mtspr	SPRN_IBAT2U, r4
481
	mtspr	SPRN_IBAT2L, r5
482
	mtspr	SPRN_IBAT3U, r6
483
	mtspr	SPRN_IBAT3L, r7
484

485
	lwz	r4, SS_IBAT+0x20(r3)
486
	lwz	r5, SS_IBAT+0x24(r3)
487
	lwz	r6, SS_IBAT+0x28(r3)
488
	lwz	r7, SS_IBAT+0x2c(r3)
489

490
	mtspr	SPRN_IBAT4U, r4
491
	mtspr	SPRN_IBAT4L, r5
492
	mtspr	SPRN_IBAT5U, r6
493
	mtspr	SPRN_IBAT5L, r7
494

495
	lwz	r4, SS_IBAT+0x30(r3)
496
	lwz	r5, SS_IBAT+0x34(r3)
497
	lwz	r6, SS_IBAT+0x38(r3)
498
	lwz	r7, SS_IBAT+0x3c(r3)
499

500
	mtspr	SPRN_IBAT6U, r4
501
	mtspr	SPRN_IBAT6L, r5
502
	mtspr	SPRN_IBAT7U, r6
503
	mtspr	SPRN_IBAT7L, r7
504

505
	lwz	r4, SS_SPRG+16(r3)
506
	lwz	r5, SS_SPRG+20(r3)
507
	lwz	r6, SS_SPRG+24(r3)
508
	lwz	r7, SS_SPRG+28(r3)
509

510
	mtspr	SPRN_SPRG4, r4
511
	mtspr	SPRN_SPRG5, r5
512
	mtspr	SPRN_SPRG6, r6
513
	mtspr	SPRN_SPRG7, r7
514

515
	lwz	r4, SS_SPRG+0(r3)
516
	lwz	r5, SS_SPRG+4(r3)
517
	lwz	r6, SS_SPRG+8(r3)
518
	lwz	r7, SS_SPRG+12(r3)
519
	lwz	r8, SS_SDR1(r3)
520

521
	mtspr	SPRN_SPRG0, r4
522
	mtspr	SPRN_SPRG1, r5
523
	mtspr	SPRN_SPRG2, r6
524
	mtspr	SPRN_SPRG3, r7
525
	mtsdr1	r8
526

527
	lwz	r4, SS_MSR(r3)
528
	lwz	r5, SS_LR(r3)
529
	lwz	r6, SS_CR(r3)
530
	lwz	r1, SS_SP(r3)
531
	lwz	r2, SS_R2(r3)
532

533
	mtsrr1	r4
534
	mtsrr0	r5
535
	mtcr	r6
536

537
	li	r4, 0
538
	mtspr	SPRN_TBWL, r4
539

540
	lwz	r4, SS_TB+0(r3)
541
	lwz	r5, SS_TB+4(r3)
542

543
	mtspr	SPRN_TBWU, r4
544
	mtspr	SPRN_TBWL, r5
545

546
	lmw	r12, SS_GPREG(r3)
547

548
	/* Kick decrementer */
549
	li	r0, 1
550
	mtdec	r0
551

552
	rfi
553
_ASM_NOKPROBE_SYMBOL(mpc83xx_deep_resume)
554

555
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