Book a Demo!
CoCalc Logo Icon
StoreFeaturesDocsShareSupportNewsAboutPoliciesSign UpSign In
torvalds
GitHub Repository: torvalds/linux
Path: blob/master/arch/powerpc/platforms/83xx/suspend.c
26481 views
1
// SPDX-License-Identifier: GPL-2.0-only
2
/*
3
* MPC83xx suspend support
4
*
5
* Author: Scott Wood <[email protected]>
6
*
7
* Copyright (c) 2006-2007 Freescale Semiconductor, Inc.
8
*/
9
10
#include <linux/pm.h>
11
#include <linux/types.h>
12
#include <linux/ioport.h>
13
#include <linux/interrupt.h>
14
#include <linux/wait.h>
15
#include <linux/sched/signal.h>
16
#include <linux/kthread.h>
17
#include <linux/freezer.h>
18
#include <linux/suspend.h>
19
#include <linux/fsl_devices.h>
20
#include <linux/of_address.h>
21
#include <linux/of_irq.h>
22
#include <linux/platform_device.h>
23
#include <linux/export.h>
24
25
#include <asm/reg.h>
26
#include <asm/io.h>
27
#include <asm/time.h>
28
#include <asm/mpc6xx.h>
29
#include <asm/switch_to.h>
30
31
#include <sysdev/fsl_soc.h>
32
33
#define PMCCR1_NEXT_STATE 0x0C /* Next state for power management */
34
#define PMCCR1_NEXT_STATE_SHIFT 2
35
#define PMCCR1_CURR_STATE 0x03 /* Current state for power management*/
36
#define IMMR_SYSCR_OFFSET 0x100
37
#define IMMR_RCW_OFFSET 0x900
38
#define RCW_PCI_HOST 0x80000000
39
40
void mpc83xx_enter_deep_sleep(phys_addr_t immrbase);
41
42
struct mpc83xx_pmc {
43
u32 config;
44
#define PMCCR_DLPEN 2 /* DDR SDRAM low power enable */
45
#define PMCCR_SLPEN 1 /* System low power enable */
46
47
u32 event;
48
u32 mask;
49
/* All but PMCI are deep-sleep only */
50
#define PMCER_GPIO 0x100
51
#define PMCER_PCI 0x080
52
#define PMCER_USB 0x040
53
#define PMCER_ETSEC1 0x020
54
#define PMCER_ETSEC2 0x010
55
#define PMCER_TIMER 0x008
56
#define PMCER_INT1 0x004
57
#define PMCER_INT2 0x002
58
#define PMCER_PMCI 0x001
59
#define PMCER_ALL 0x1FF
60
61
/* deep-sleep only */
62
u32 config1;
63
#define PMCCR1_USE_STATE 0x80000000
64
#define PMCCR1_PME_EN 0x00000080
65
#define PMCCR1_ASSERT_PME 0x00000040
66
#define PMCCR1_POWER_OFF 0x00000020
67
68
/* deep-sleep only */
69
u32 config2;
70
};
71
72
struct mpc83xx_rcw {
73
u32 rcwlr;
74
u32 rcwhr;
75
};
76
77
struct mpc83xx_clock {
78
u32 spmr;
79
u32 occr;
80
u32 sccr;
81
};
82
83
struct mpc83xx_syscr {
84
__be32 sgprl;
85
__be32 sgprh;
86
__be32 spridr;
87
__be32 :32;
88
__be32 spcr;
89
__be32 sicrl;
90
__be32 sicrh;
91
};
92
93
struct mpc83xx_saved {
94
u32 sicrl;
95
u32 sicrh;
96
u32 sccr;
97
};
98
99
struct pmc_type {
100
int has_deep_sleep;
101
};
102
103
static int has_deep_sleep, deep_sleeping;
104
static int pmc_irq;
105
static struct mpc83xx_pmc __iomem *pmc_regs;
106
static struct mpc83xx_clock __iomem *clock_regs;
107
static struct mpc83xx_syscr __iomem *syscr_regs;
108
static struct mpc83xx_saved saved_regs;
109
static int is_pci_agent, wake_from_pci;
110
static phys_addr_t immrbase;
111
static int pci_pm_state;
112
static DECLARE_WAIT_QUEUE_HEAD(agent_wq);
113
114
int fsl_deep_sleep(void)
115
{
116
return deep_sleeping;
117
}
118
EXPORT_SYMBOL(fsl_deep_sleep);
119
120
static int mpc83xx_change_state(void)
121
{
122
u32 curr_state;
123
u32 reg_cfg1 = in_be32(&pmc_regs->config1);
124
125
if (is_pci_agent) {
126
pci_pm_state = (reg_cfg1 & PMCCR1_NEXT_STATE) >>
127
PMCCR1_NEXT_STATE_SHIFT;
128
curr_state = reg_cfg1 & PMCCR1_CURR_STATE;
129
130
if (curr_state != pci_pm_state) {
131
reg_cfg1 &= ~PMCCR1_CURR_STATE;
132
reg_cfg1 |= pci_pm_state;
133
out_be32(&pmc_regs->config1, reg_cfg1);
134
135
wake_up(&agent_wq);
136
return 1;
137
}
138
}
139
140
return 0;
141
}
142
143
static irqreturn_t pmc_irq_handler(int irq, void *dev_id)
144
{
145
u32 event = in_be32(&pmc_regs->event);
146
int ret = IRQ_NONE;
147
148
if (mpc83xx_change_state())
149
ret = IRQ_HANDLED;
150
151
if (event) {
152
out_be32(&pmc_regs->event, event);
153
ret = IRQ_HANDLED;
154
}
155
156
return ret;
157
}
158
159
static void mpc83xx_suspend_restore_regs(void)
160
{
161
out_be32(&syscr_regs->sicrl, saved_regs.sicrl);
162
out_be32(&syscr_regs->sicrh, saved_regs.sicrh);
163
out_be32(&clock_regs->sccr, saved_regs.sccr);
164
}
165
166
static void mpc83xx_suspend_save_regs(void)
167
{
168
saved_regs.sicrl = in_be32(&syscr_regs->sicrl);
169
saved_regs.sicrh = in_be32(&syscr_regs->sicrh);
170
saved_regs.sccr = in_be32(&clock_regs->sccr);
171
}
172
173
static int mpc83xx_suspend_enter(suspend_state_t state)
174
{
175
int ret = -EAGAIN;
176
177
/* Don't go to sleep if there's a race where pci_pm_state changes
178
* between the agent thread checking it and the PM code disabling
179
* interrupts.
180
*/
181
if (wake_from_pci) {
182
if (pci_pm_state != (deep_sleeping ? 3 : 2))
183
goto out;
184
185
out_be32(&pmc_regs->config1,
186
in_be32(&pmc_regs->config1) | PMCCR1_PME_EN);
187
}
188
189
/* Put the system into low-power mode and the RAM
190
* into self-refresh mode once the core goes to
191
* sleep.
192
*/
193
194
out_be32(&pmc_regs->config, PMCCR_SLPEN | PMCCR_DLPEN);
195
196
/* If it has deep sleep (i.e. it's an 831x or compatible),
197
* disable power to the core upon entering sleep mode. This will
198
* require going through the boot firmware upon a wakeup event.
199
*/
200
201
if (deep_sleeping) {
202
mpc83xx_suspend_save_regs();
203
204
out_be32(&pmc_regs->mask, PMCER_ALL);
205
206
out_be32(&pmc_regs->config1,
207
in_be32(&pmc_regs->config1) | PMCCR1_POWER_OFF);
208
209
if (IS_ENABLED(CONFIG_PPC_FPU))
210
enable_kernel_fp();
211
212
mpc83xx_enter_deep_sleep(immrbase);
213
214
out_be32(&pmc_regs->config1,
215
in_be32(&pmc_regs->config1) & ~PMCCR1_POWER_OFF);
216
217
out_be32(&pmc_regs->mask, PMCER_PMCI);
218
219
mpc83xx_suspend_restore_regs();
220
} else {
221
out_be32(&pmc_regs->mask, PMCER_PMCI);
222
223
mpc6xx_enter_standby();
224
}
225
226
ret = 0;
227
228
out:
229
out_be32(&pmc_regs->config1,
230
in_be32(&pmc_regs->config1) & ~PMCCR1_PME_EN);
231
232
return ret;
233
}
234
235
static void mpc83xx_suspend_end(void)
236
{
237
deep_sleeping = 0;
238
}
239
240
static int mpc83xx_suspend_valid(suspend_state_t state)
241
{
242
return state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM;
243
}
244
245
static int mpc83xx_suspend_begin(suspend_state_t state)
246
{
247
switch (state) {
248
case PM_SUSPEND_STANDBY:
249
deep_sleeping = 0;
250
return 0;
251
252
case PM_SUSPEND_MEM:
253
if (has_deep_sleep)
254
deep_sleeping = 1;
255
256
return 0;
257
258
default:
259
return -EINVAL;
260
}
261
}
262
263
static int agent_thread_fn(void *data)
264
{
265
set_freezable();
266
267
while (1) {
268
wait_event_freezable(agent_wq, pci_pm_state >= 2);
269
270
if (signal_pending(current) || pci_pm_state < 2)
271
continue;
272
273
/* With a preemptible kernel (or SMP), this could race with
274
* a userspace-driven suspend request. It's probably best
275
* to avoid mixing the two with such a configuration (or
276
* else fix it by adding a mutex to state_store that we can
277
* synchronize with).
278
*/
279
280
wake_from_pci = 1;
281
282
pm_suspend(pci_pm_state == 3 ? PM_SUSPEND_MEM :
283
PM_SUSPEND_STANDBY);
284
285
wake_from_pci = 0;
286
}
287
288
return 0;
289
}
290
291
static void mpc83xx_set_agent(void)
292
{
293
out_be32(&pmc_regs->config1, PMCCR1_USE_STATE);
294
out_be32(&pmc_regs->mask, PMCER_PMCI);
295
296
kthread_run(agent_thread_fn, NULL, "PCI power mgt");
297
}
298
299
static int mpc83xx_is_pci_agent(void)
300
{
301
struct mpc83xx_rcw __iomem *rcw_regs;
302
int ret;
303
304
rcw_regs = ioremap(get_immrbase() + IMMR_RCW_OFFSET,
305
sizeof(struct mpc83xx_rcw));
306
307
if (!rcw_regs)
308
return -ENOMEM;
309
310
ret = !(in_be32(&rcw_regs->rcwhr) & RCW_PCI_HOST);
311
312
iounmap(rcw_regs);
313
return ret;
314
}
315
316
static const struct platform_suspend_ops mpc83xx_suspend_ops = {
317
.valid = mpc83xx_suspend_valid,
318
.begin = mpc83xx_suspend_begin,
319
.enter = mpc83xx_suspend_enter,
320
.end = mpc83xx_suspend_end,
321
};
322
323
static struct pmc_type pmc_types[] = {
324
{
325
.has_deep_sleep = 1,
326
},
327
{
328
.has_deep_sleep = 0,
329
}
330
};
331
332
static const struct of_device_id pmc_match[] = {
333
{
334
.compatible = "fsl,mpc8313-pmc",
335
.data = &pmc_types[0],
336
},
337
{
338
.compatible = "fsl,mpc8349-pmc",
339
.data = &pmc_types[1],
340
},
341
{}
342
};
343
344
static int pmc_probe(struct platform_device *ofdev)
345
{
346
struct device_node *np = ofdev->dev.of_node;
347
struct resource res;
348
const struct pmc_type *type;
349
int ret = 0;
350
351
type = of_device_get_match_data(&ofdev->dev);
352
if (!type)
353
return -EINVAL;
354
355
if (!of_device_is_available(np))
356
return -ENODEV;
357
358
has_deep_sleep = type->has_deep_sleep;
359
immrbase = get_immrbase();
360
361
is_pci_agent = mpc83xx_is_pci_agent();
362
if (is_pci_agent < 0)
363
return is_pci_agent;
364
365
ret = of_address_to_resource(np, 0, &res);
366
if (ret)
367
return -ENODEV;
368
369
pmc_irq = irq_of_parse_and_map(np, 0);
370
if (pmc_irq) {
371
ret = request_irq(pmc_irq, pmc_irq_handler, IRQF_SHARED,
372
"pmc", ofdev);
373
374
if (ret)
375
return -EBUSY;
376
}
377
378
pmc_regs = ioremap(res.start, sizeof(*pmc_regs));
379
380
if (!pmc_regs) {
381
ret = -ENOMEM;
382
goto out;
383
}
384
385
ret = of_address_to_resource(np, 1, &res);
386
if (ret) {
387
ret = -ENODEV;
388
goto out_pmc;
389
}
390
391
clock_regs = ioremap(res.start, sizeof(*clock_regs));
392
393
if (!clock_regs) {
394
ret = -ENOMEM;
395
goto out_pmc;
396
}
397
398
if (has_deep_sleep) {
399
syscr_regs = ioremap(immrbase + IMMR_SYSCR_OFFSET,
400
sizeof(*syscr_regs));
401
if (!syscr_regs) {
402
ret = -ENOMEM;
403
goto out_syscr;
404
}
405
}
406
407
if (is_pci_agent)
408
mpc83xx_set_agent();
409
410
suspend_set_ops(&mpc83xx_suspend_ops);
411
return 0;
412
413
out_syscr:
414
iounmap(clock_regs);
415
out_pmc:
416
iounmap(pmc_regs);
417
out:
418
if (pmc_irq)
419
free_irq(pmc_irq, ofdev);
420
421
return ret;
422
}
423
424
static struct platform_driver pmc_driver = {
425
.driver = {
426
.name = "mpc83xx-pmc",
427
.of_match_table = pmc_match,
428
.suppress_bind_attrs = true,
429
},
430
.probe = pmc_probe,
431
};
432
433
builtin_platform_driver(pmc_driver);
434
435