Path: blob/master/arch/powerpc/platforms/powermac/udbg_scc.c
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// SPDX-License-Identifier: GPL-2.0-or-later1/*2* udbg for zilog scc ports as found on Apple PowerMacs3*4* Copyright (C) 2001-2005 PPC 64 Team, IBM Corp5*/6#include <linux/types.h>7#include <linux/of.h>8#include <asm/udbg.h>9#include <asm/processor.h>10#include <asm/io.h>11#include <asm/pmac_feature.h>1213extern u8 real_readb(volatile u8 __iomem *addr);14extern void real_writeb(u8 data, volatile u8 __iomem *addr);1516#define SCC_TXRDY 417#define SCC_RXRDY 11819static volatile u8 __iomem *sccc;20static volatile u8 __iomem *sccd;2122static void udbg_scc_putc(char c)23{24if (sccc) {25while ((in_8(sccc) & SCC_TXRDY) == 0)26;27out_8(sccd, c);28if (c == '\n')29udbg_scc_putc('\r');30}31}3233static int udbg_scc_getc_poll(void)34{35if (sccc) {36if ((in_8(sccc) & SCC_RXRDY) != 0)37return in_8(sccd);38else39return -1;40}41return -1;42}4344static int udbg_scc_getc(void)45{46if (sccc) {47while ((in_8(sccc) & SCC_RXRDY) == 0)48;49return in_8(sccd);50}51return -1;52}5354static unsigned char scc_inittab[] = {5513, 0, /* set baud rate divisor */5612, 0,5714, 1, /* baud rate gen enable, src=rtxc */5811, 0x50, /* clocks = br gen */595, 0xea, /* tx 8 bits, assert DTR & RTS */604, 0x46, /* x16 clock, 1 stop */613, 0xc1, /* rx enable, 8 bits */62};6364void __init udbg_scc_init(int force_scc)65{66const u32 *reg;67unsigned long addr;68struct device_node *stdout = NULL, *escc = NULL, *macio = NULL;69struct device_node *ch, *ch_def = NULL, *ch_a = NULL;70const char *path;71int i;7273escc = of_find_node_by_name(NULL, "escc");74if (escc == NULL)75goto bail;76macio = of_get_parent(escc);77if (macio == NULL)78goto bail;79path = of_get_property(of_chosen, "linux,stdout-path", NULL);80if (path != NULL)81stdout = of_find_node_by_path(path);82for_each_child_of_node(escc, ch) {83if (ch == stdout) {84of_node_put(ch_def);85ch_def = of_node_get(ch);86}87if (of_node_name_eq(ch, "ch-a")) {88of_node_put(ch_a);89ch_a = of_node_get(ch);90}91}92if (ch_def == NULL && !force_scc)93goto bail;9495ch = ch_def ? ch_def : ch_a;9697/* Get address within mac-io ASIC */98reg = of_get_property(escc, "reg", NULL);99if (reg == NULL)100goto bail;101addr = reg[0];102103/* Get address of mac-io PCI itself */104reg = of_get_property(macio, "assigned-addresses", NULL);105if (reg == NULL)106goto bail;107addr += reg[2];108109/* Lock the serial port */110pmac_call_feature(PMAC_FTR_SCC_ENABLE, ch,111PMAC_SCC_ASYNC | PMAC_SCC_FLAG_XMON, 1);112113if (ch == ch_a)114addr += 0x20;115sccc = ioremap(addr & PAGE_MASK, PAGE_SIZE) ;116sccc += addr & ~PAGE_MASK;117sccd = sccc + 0x10;118119mb();120121for (i = 20000; i != 0; --i)122in_8(sccc);123out_8(sccc, 0x09); /* reset A or B side */124out_8(sccc, 0xc0);125126/* If SCC was the OF output port, read the BRG value, else127* Setup for 38400 or 57600 8N1 depending on the machine128*/129if (ch_def != NULL) {130out_8(sccc, 13);131scc_inittab[1] = in_8(sccc);132out_8(sccc, 12);133scc_inittab[3] = in_8(sccc);134} else if (of_machine_is_compatible("RackMac1,1")135|| of_machine_is_compatible("RackMac1,2")136|| of_machine_is_compatible("MacRISC4")) {137/* Xserves and G5s default to 57600 */138scc_inittab[1] = 0;139scc_inittab[3] = 0;140} else {141/* Others default to 38400 */142scc_inittab[1] = 0;143scc_inittab[3] = 1;144}145146for (i = 0; i < sizeof(scc_inittab); ++i)147out_8(sccc, scc_inittab[i]);148149150udbg_putc = udbg_scc_putc;151udbg_getc = udbg_scc_getc;152udbg_getc_poll = udbg_scc_getc_poll;153154udbg_puts("Hello World !\n");155156bail:157of_node_put(macio);158of_node_put(escc);159of_node_put(stdout);160of_node_put(ch_def);161of_node_put(ch_a);162}163164#ifdef CONFIG_PPC64165static void udbg_real_scc_putc(char c)166{167while ((real_readb(sccc) & SCC_TXRDY) == 0)168;169real_writeb(c, sccd);170if (c == '\n')171udbg_real_scc_putc('\r');172}173174void __init udbg_init_pmac_realmode(void)175{176sccc = (volatile u8 __iomem *)0x80013020ul;177sccd = (volatile u8 __iomem *)0x80013030ul;178179udbg_putc = udbg_real_scc_putc;180udbg_getc = NULL;181udbg_getc_poll = NULL;182}183#endif /* CONFIG_PPC64 */184185186