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torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/arch/powerpc/sysdev/indirect_pci.c
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// SPDX-License-Identifier: GPL-2.0-or-later

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/*

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 * Support for indirect PCI bridges.

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 *

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 * Copyright (C) 1998 Gabriel Paubert.

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 */

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#include <linux/kernel.h>

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#include <linux/pci.h>

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#include <linux/delay.h>

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#include <linux/string.h>

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#include <linux/init.h>

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#include <asm/io.h>

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#include <asm/pci-bridge.h>

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#include <asm/machdep.h>

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int __indirect_read_config(struct pci_controller *hose,

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			   unsigned char bus_number, unsigned int devfn,

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			   int offset, int len, u32 *val)

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{

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	volatile void __iomem *cfg_data;

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	u8 cfg_type = 0;

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	u32 bus_no, reg;

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	if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) {

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		if (bus_number != hose->first_busno)

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			return PCIBIOS_DEVICE_NOT_FOUND;

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		if (devfn != 0)

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			return PCIBIOS_DEVICE_NOT_FOUND;

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	}

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	if (ppc_md.pci_exclude_device)

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		if (ppc_md.pci_exclude_device(hose, bus_number, devfn))

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			return PCIBIOS_DEVICE_NOT_FOUND;

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	if (hose->indirect_type & PPC_INDIRECT_TYPE_SET_CFG_TYPE)

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		if (bus_number != hose->first_busno)

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			cfg_type = 1;

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	bus_no = (bus_number == hose->first_busno) ?

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			hose->self_busno : bus_number;

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	if (hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG)

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		reg = ((offset & 0xf00) << 16) | (offset & 0xfc);

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	else

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		reg = offset & 0xfc;

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	if (hose->indirect_type & PPC_INDIRECT_TYPE_BIG_ENDIAN)

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		out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |

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			 (devfn << 8) | reg | cfg_type));

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	else

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		out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |

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			 (devfn << 8) | reg | cfg_type));

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	/*

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	 * Note: the caller has already checked that offset is

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	 * suitably aligned and that len is 1, 2 or 4.

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	 */

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	cfg_data = hose->cfg_data + (offset & 3);

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	switch (len) {

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	case 1:

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		*val = in_8(cfg_data);

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		break;

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	case 2:

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		*val = in_le16(cfg_data);

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		break;

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	default:

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		*val = in_le32(cfg_data);

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		break;

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	}

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	return PCIBIOS_SUCCESSFUL;

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}

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int indirect_read_config(struct pci_bus *bus, unsigned int devfn,

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			 int offset, int len, u32 *val)

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{

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	struct pci_controller *hose = pci_bus_to_host(bus);

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	return __indirect_read_config(hose, bus->number, devfn, offset, len,

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				      val);

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}

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int indirect_write_config(struct pci_bus *bus, unsigned int devfn,

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			  int offset, int len, u32 val)

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{

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	struct pci_controller *hose = pci_bus_to_host(bus);

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	volatile void __iomem *cfg_data;

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	u8 cfg_type = 0;

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	u32 bus_no, reg;

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	if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) {

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		if (bus->number != hose->first_busno)

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			return PCIBIOS_DEVICE_NOT_FOUND;

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		if (devfn != 0)

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			return PCIBIOS_DEVICE_NOT_FOUND;

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	}

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	if (ppc_md.pci_exclude_device)

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		if (ppc_md.pci_exclude_device(hose, bus->number, devfn))

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			return PCIBIOS_DEVICE_NOT_FOUND;

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	if (hose->indirect_type & PPC_INDIRECT_TYPE_SET_CFG_TYPE)

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		if (bus->number != hose->first_busno)

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			cfg_type = 1;

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	bus_no = (bus->number == hose->first_busno) ?

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			hose->self_busno : bus->number;

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	if (hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG)

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		reg = ((offset & 0xf00) << 16) | (offset & 0xfc);

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	else

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		reg = offset & 0xfc;

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	if (hose->indirect_type & PPC_INDIRECT_TYPE_BIG_ENDIAN)

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		out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |

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			 (devfn << 8) | reg | cfg_type));

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	else

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		out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |

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			 (devfn << 8) | reg | cfg_type));

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	/* suppress setting of PCI_PRIMARY_BUS */

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	if (hose->indirect_type & PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS)

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		if ((offset == PCI_PRIMARY_BUS) &&

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			(bus->number == hose->first_busno))

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		val &= 0xffffff00;

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	/* Workaround for PCI_28 Errata in 440EPx/GRx */

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	if ((hose->indirect_type & PPC_INDIRECT_TYPE_BROKEN_MRM) &&

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			offset == PCI_CACHE_LINE_SIZE) {

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		val = 0;

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	}

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	/*

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	 * Note: the caller has already checked that offset is

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	 * suitably aligned and that len is 1, 2 or 4.

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	 */

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	cfg_data = hose->cfg_data + (offset & 3);

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	switch (len) {

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	case 1:

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		out_8(cfg_data, val);

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		break;

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	case 2:

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		out_le16(cfg_data, val);

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		break;

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	default:

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		out_le32(cfg_data, val);

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		break;

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	}

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	return PCIBIOS_SUCCESSFUL;

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}

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static struct pci_ops indirect_pci_ops =

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{

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	.read = indirect_read_config,

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	.write = indirect_write_config,

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};

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void setup_indirect_pci(struct pci_controller *hose, resource_size_t cfg_addr,

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			resource_size_t cfg_data, u32 flags)

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{

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	resource_size_t base = cfg_addr & PAGE_MASK;

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	void __iomem *mbase;

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	mbase = ioremap(base, PAGE_SIZE);

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	hose->cfg_addr = mbase + (cfg_addr & ~PAGE_MASK);

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	if ((cfg_data & PAGE_MASK) != base)

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		mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE);

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	hose->cfg_data = mbase + (cfg_data & ~PAGE_MASK);

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	hose->ops = &indirect_pci_ops;

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	hose->indirect_type = flags;

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}

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