dr1v90.dtsi

// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
 * Copyright (C) 2025 Junhui Liu <[email protected]>
 */

/dts-v1/;
/ {
	#address-cells = <2>;
	#size-cells = <2>;
	model = "Anlogic DR1V90";
	compatible = "anlogic,dr1v90";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		timebase-frequency = <800000000>;

		cpu@0 {
			compatible = "nuclei,ux900", "riscv";
			d-cache-block-size = <64>;
			d-cache-sets = <256>;
			d-cache-size = <32768>;
			device_type = "cpu";
			i-cache-block-size = <64>;
			i-cache-sets = <256>;
			i-cache-size = <32768>;
			mmu-type = "riscv,sv39";
			reg = <0>;
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b",
					       "zba", "zbb", "zbc", "zbkc", "zbs",
					       "zicntr", "zicsr", "zifencei",
					       "zihintpause", "zihpm";

			cpu0_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				#interrupt-cells = <1>;
				interrupt-controller;
			};
		};
	};

	soc {
		compatible = "simple-bus";
		interrupt-parent = <&plic>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		aclint_mswi: interrupt-controller@68031000 {
			compatible = "anlogic,dr1v90-aclint-mswi", "nuclei,ux900-aclint-mswi";
			reg = <0x0 0x68031000 0x0 0x4000>;
			interrupts-extended = <&cpu0_intc 3>;
		};

		aclint_mtimer: timer@68035000 {
			compatible = "anlogic,dr1v90-aclint-mtimer", "nuclei,ux900-aclint-mtimer";
			reg = <0x0 0x68035000 0x0 0x8000>;
			reg-names = "mtimecmp";
			interrupts-extended = <&cpu0_intc 7>;
		};

		aclint_sswi: interrupt-controller@6803d000 {
			compatible = "anlogic,dr1v90-aclint-sswi", "nuclei,ux900-aclint-sswi";
			reg = <0x0 0x6803d000 0x0 0x3000>;
			#interrupt-cells = <0>;
			interrupt-controller;
			interrupts-extended = <&cpu0_intc 1>;
		};

		plic: interrupt-controller@6c000000 {
			compatible = "anlogic,dr1v90-plic", "sifive,plic-1.0.0";
			reg = <0x0 0x6c000000 0x0 0x4000000>;
			#address-cells = <0>;
			#interrupt-cells = <1>;
			interrupt-controller;
			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
			riscv,ndev = <150>;
		};

		uart0: serial@f8400000 {
			compatible = "anlogic,dr1v90-uart", "snps,dw-apb-uart";
			reg = <0x0 0xf8400000 0x0 0x1000>;
			clock-frequency = <50000000>;
			interrupts = <71>;
			reg-io-width = <4>;
			reg-shift = <2>;
			status = "disabled";
		};

		uart1: serial@f8401000 {
			compatible = "anlogic,dr1v90-uart", "snps,dw-apb-uart";
			reg = <0x0 0xf8401000 0x0 0x1000>;
			clock-frequency = <50000000>;
			interrupts = <72>;
			reg-io-width = <4>;
			reg-shift = <2>;
			status = "disabled";
		};
	};
};