Path: blob/master/arch/riscv/boot/dts/sophgo/cv180x.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Copyright (C) 2023 Jisheng Zhang <[email protected]> * Copyright (C) 2023 Inochi Amaoto <[email protected]> */ #include <dt-bindings/clock/sophgo,cv1800.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> #include "cv18xx-reset.h" / { #address-cells = <1>; #size-cells = <1>; osc: oscillator { compatible = "fixed-clock"; clock-output-names = "osc_25m"; #clock-cells = <0>; }; soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; rst: reset-controller@3003000 { compatible = "sophgo,cv1800b-reset"; reg = <0x3003000 0x1000>; #reset-cells = <1>; }; mdio: mdio-mux@3009800 { compatible = "mdio-mux-mmioreg", "mdio-mux"; reg = <0x3009800 0x4>; #address-cells = <1>; #size-cells = <0>; mdio-parent-bus = <&gmac0_mdio>; mux-mask = <0x80>; status = "disabled"; internal_mdio: mdio@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; internal_ephy: phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; }; }; external_mdio: mdio@80 { #address-cells = <1>; #size-cells = <0>; reg = <0x80>; }; }; gpio0: gpio@3020000 { compatible = "snps,dw-apb-gpio"; reg = <0x3020000 0x1000>; #address-cells = <1>; #size-cells = <0>; resets = <&rst RST_GPIO0>; porta: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; ngpios = <32>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; interrupts = <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>; }; }; gpio1: gpio@3021000 { compatible = "snps,dw-apb-gpio"; reg = <0x3021000 0x1000>; #address-cells = <1>; #size-cells = <0>; resets = <&rst RST_GPIO1>; portb: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; ngpios = <32>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; interrupts = <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>; }; }; gpio2: gpio@3022000 { compatible = "snps,dw-apb-gpio"; reg = <0x3022000 0x1000>; #address-cells = <1>; #size-cells = <0>; resets = <&rst RST_GPIO2>; portc: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; ngpios = <32>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_LEVEL_HIGH>; }; }; gpio3: gpio@3023000 { compatible = "snps,dw-apb-gpio"; reg = <0x3023000 0x1000>; #address-cells = <1>; #size-cells = <0>; resets = <&rst RST_GPIO3>; portd: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; ngpios = <32>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; interrupts = <SOC_PERIPHERAL_IRQ(47) IRQ_TYPE_LEVEL_HIGH>; }; }; saradc: adc@30f0000 { compatible = "sophgo,cv1800b-saradc"; reg = <0x030f0000 0x1000>; clocks = <&clk CLK_SARADC>; interrupts = <SOC_PERIPHERAL_IRQ(84) IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; channel@0 { reg = <0>; }; channel@1 { reg = <1>; }; channel@2 { reg = <2>; }; }; i2c0: i2c@4000000 { compatible = "snps,designware-i2c"; reg = <0x04000000 0x10000>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>; clock-names = "ref", "pclk"; interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>; resets = <&rst RST_I2C0>; status = "disabled"; }; i2c1: i2c@4010000 { compatible = "snps,designware-i2c"; reg = <0x04010000 0x10000>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>; clock-names = "ref", "pclk"; interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>; resets = <&rst RST_I2C1>; status = "disabled"; }; i2c2: i2c@4020000 { compatible = "snps,designware-i2c"; reg = <0x04020000 0x10000>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>; clock-names = "ref", "pclk"; interrupts = <SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_LEVEL_HIGH>; resets = <&rst RST_I2C2>; status = "disabled"; }; i2c3: i2c@4030000 { compatible = "snps,designware-i2c"; reg = <0x04030000 0x10000>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>; clock-names = "ref", "pclk"; interrupts = <SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_LEVEL_HIGH>; resets = <&rst RST_I2C3>; status = "disabled"; }; i2c4: i2c@4040000 { compatible = "snps,designware-i2c"; reg = <0x04040000 0x10000>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>; clock-names = "ref", "pclk"; interrupts = <SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_LEVEL_HIGH>; resets = <&rst RST_I2C4>; status = "disabled"; }; gmac0: ethernet@4070000 { compatible = "sophgo,cv1800b-dwmac", "snps,dwmac-3.70a"; reg = <0x04070000 0x10000>; clocks = <&clk CLK_AXI4_ETH0>, <&clk CLK_ETH0_500M>; clock-names = "stmmaceth", "ptp_ref"; interrupts = <SOC_PERIPHERAL_IRQ(15) IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; phy-handle = <&internal_ephy>; phy-mode = "internal"; resets = <&rst RST_ETH0>; reset-names = "stmmaceth"; rx-fifo-depth = <8192>; tx-fifo-depth = <8192>; snps,multicast-filter-bins = <0>; snps,perfect-filter-entries = <1>; snps,aal; snps,txpbl = <8>; snps,rxpbl = <8>; snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; snps,axi-config = <&gmac0_stmmac_axi_setup>; status = "disabled"; gmac0_mdio: mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; }; gmac0_mtl_rx_setup: rx-queues-config { snps,rx-queues-to-use = <1>; queue0 {}; }; gmac0_mtl_tx_setup: tx-queues-config { snps,tx-queues-to-use = <1>; queue0 {}; }; gmac0_stmmac_axi_setup: stmmac-axi-config { snps,blen = <16 8 4 0 0 0 0>; snps,rd_osr_lmt = <2>; snps,wr_osr_lmt = <1>; }; }; uart0: serial@4140000 { compatible = "snps,dw-apb-uart"; reg = <0x04140000 0x100>; interrupts = <SOC_PERIPHERAL_IRQ(28) IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>; clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; resets = <&rst RST_UART0>; status = "disabled"; }; uart1: serial@4150000 { compatible = "snps,dw-apb-uart"; reg = <0x04150000 0x100>; interrupts = <SOC_PERIPHERAL_IRQ(29) IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>; clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; resets = <&rst RST_UART1>; status = "disabled"; }; uart2: serial@4160000 { compatible = "snps,dw-apb-uart"; reg = <0x04160000 0x100>; interrupts = <SOC_PERIPHERAL_IRQ(30) IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>; clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; resets = <&rst RST_UART2>; status = "disabled"; }; uart3: serial@4170000 { compatible = "snps,dw-apb-uart"; reg = <0x04170000 0x100>; interrupts = <SOC_PERIPHERAL_IRQ(31) IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>; clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; resets = <&rst RST_UART3>; status = "disabled"; }; spi0: spi@4180000 { compatible = "snps,dw-apb-ssi"; reg = <0x04180000 0x10000>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>; clock-names = "ssi_clk", "pclk"; interrupts = <SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_LEVEL_HIGH>; resets = <&rst RST_SPI0>; status = "disabled"; }; spi1: spi@4190000 { compatible = "snps,dw-apb-ssi"; reg = <0x04190000 0x10000>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>; clock-names = "ssi_clk", "pclk"; interrupts = <SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_LEVEL_HIGH>; resets = <&rst RST_SPI1>; status = "disabled"; }; spi2: spi@41a0000 { compatible = "snps,dw-apb-ssi"; reg = <0x041a0000 0x10000>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>; clock-names = "ssi_clk", "pclk"; interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>; resets = <&rst RST_SPI2>; status = "disabled"; }; spi3: spi@41b0000 { compatible = "snps,dw-apb-ssi"; reg = <0x041b0000 0x10000>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>; clock-names = "ssi_clk", "pclk"; interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>; resets = <&rst RST_SPI3>; status = "disabled"; }; uart4: serial@41c0000 { compatible = "snps,dw-apb-uart"; reg = <0x041c0000 0x100>; interrupts = <SOC_PERIPHERAL_IRQ(32) IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>; clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; resets = <&rst RST_UART4>; status = "disabled"; }; sdhci0: mmc@4310000 { compatible = "sophgo,cv1800b-dwcmshc"; reg = <0x4310000 0x1000>; interrupts = <SOC_PERIPHERAL_IRQ(20) IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk CLK_AXI4_SD0>, <&clk CLK_SD0>; clock-names = "core", "bus"; status = "disabled"; }; sdhci1: mmc@4320000 { compatible = "sophgo,cv1800b-dwcmshc"; reg = <0x4320000 0x1000>; interrupts = <SOC_PERIPHERAL_IRQ(22) IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk CLK_AXI4_SD1>, <&clk CLK_SD1>; clock-names = "core", "bus"; status = "disabled"; }; dmac: dma-controller@4330000 { compatible = "snps,axi-dma-1.01a"; reg = <0x04330000 0x1000>; interrupts = <SOC_PERIPHERAL_IRQ(13) IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>; clock-names = "core-clk", "cfgr-clk"; #dma-cells = <1>; dma-channels = <8>; snps,block-size = <1024 1024 1024 1024 1024 1024 1024 1024>; snps,priority = <0 1 2 3 4 5 6 7>; snps,dma-masters = <2>; snps,data-width = <2>; status = "disabled"; }; rtc@5025000 { compatible = "sophgo,cv1800b-rtc", "syscon"; reg = <0x5025000 0x2000>; interrupts = <SOC_PERIPHERAL_IRQ(1) IRQ_TYPE_LEVEL_HIGH>, <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>, <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "alarm", "longpress", "vbat"; clocks = <&clk CLK_RTC_25M>, <&clk CLK_SRC_RTC_SYS_0>; clock-names = "rtc", "mcu"; }; }; };