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torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/arch/riscv/boot/dts/sophgo/cv18xx-reset.h
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */

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/*

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 * Copyright (C) 2025 Inochi Amaoto <[email protected]>

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 */

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#ifndef _SOPHGO_CV18XX_RESET

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#define _SOPHGO_CV18XX_RESET

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#define RST_DDR				2

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#define RST_H264C			3

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#define RST_JPEG			4

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#define RST_H265C			5

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#define RST_VIPSYS			6

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#define RST_TDMA			7

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#define RST_TPU				8

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#define RST_TPUSYS			9

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#define RST_USB				11

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#define RST_ETH0			12

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#define RST_ETH1			13

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#define RST_NAND			14

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#define RST_EMMC			15

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#define RST_SD0				16

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#define RST_SDMA			18

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#define RST_I2S0			19

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#define RST_I2S1			20

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#define RST_I2S2			21

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#define RST_I2S3			22

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#define RST_UART0			23

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#define RST_UART1			24

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#define RST_UART2			25

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#define RST_UART3			26

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#define RST_I2C0			27

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#define RST_I2C1			28

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#define RST_I2C2			29

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#define RST_I2C3			30

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#define RST_I2C4			31

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#define RST_PWM0			32

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#define RST_PWM1			33

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#define RST_PWM2			34

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#define RST_PWM3			35

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#define RST_SPI0			40

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#define RST_SPI1			41

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#define RST_SPI2			42

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#define RST_SPI3			43

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#define RST_GPIO0			44

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#define RST_GPIO1			45

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#define RST_GPIO2			46

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#define RST_EFUSE			47

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#define RST_WDT				48

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#define RST_AHB_ROM			49

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#define RST_SPIC			50

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#define RST_TEMPSEN			51

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#define RST_SARADC			52

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#define RST_COMBO_PHY0			58

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#define RST_SPI_NAND			61

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#define RST_SE				62

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#define RST_UART4			74

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#define RST_GPIO3			75

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#define RST_SYSTEM			76

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#define RST_TIMER			77

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#define RST_TIMER0			78

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#define RST_TIMER1			79

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#define RST_TIMER2			80

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#define RST_TIMER3			81

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#define RST_TIMER4			82

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#define RST_TIMER5			83

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#define RST_TIMER6			84

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#define RST_TIMER7			85

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#define RST_WGN0			86

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#define RST_WGN1			87

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#define RST_WGN2			88

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#define RST_KEYSCAN			89

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#define RST_AUDDAC			91

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#define RST_AUDDAC_APB			92

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#define RST_AUDADC			93

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#define RST_VCSYS			95

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#define RST_ETHPHY			96

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#define RST_ETHPHY_APB			97

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#define RST_AUDSRC			98

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#define RST_VIP_CAM0			99

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#define RST_WDT1			100

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#define RST_WDT2			101

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#define RST_AUTOCLEAR_CPUCORE0		256

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#define RST_AUTOCLEAR_CPUCORE1		257

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#define RST_AUTOCLEAR_CPUCORE2		258

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#define RST_AUTOCLEAR_CPUCORE3		259

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#define RST_AUTOCLEAR_CPUSYS0		260

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#define RST_AUTOCLEAR_CPUSYS1		261

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#define RST_AUTOCLEAR_CPUSYS2		262

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#define RST_CPUCORE0			288

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#define RST_CPUCORE1			289

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#define RST_CPUCORE2			290

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#define RST_CPUCORE3			291

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#define RST_CPUSYS0			292

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#define RST_CPUSYS1			293

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#define RST_CPUSYS2			294

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#endif /* _SOPHGO_CV18XX_RESET */

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