// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd * Copyright (c) 2026 Guodong Xu <[email protected]> */ #include <dt-bindings/interrupt-controller/irq.h> /dts-v1/; / { #address-cells = <2>; #size-cells = <2>; model = "SpacemiT K3"; compatible = "spacemit,k3"; cpus: cpus { #address-cells = <1>; #size-cells = <0>; timebase-frequency = <24000000>; cpu_0: cpu@0 { compatible = "spacemit,x100", "riscv"; device_type = "cpu"; reg = <0>; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", "sha", "shcounterenw", "shgatpa", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smaia", "smstateen", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "ssnpm", "ssstateen", "sstc", "sstvala", "sstvecd", "ssu64xl", "svade", "svinval", "svnapot", "svpbmt", "za64rs", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfbfmin", "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkt", "zvbb", "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <256>; d-cache-block-size = <64>; d-cache-size = <65536>; d-cache-sets = <256>; next-level-cache = <&l2_cache0>; mmu-type = "riscv,sv39"; cpu0_intc: interrupt-controller { compatible = "riscv,cpu-intc"; #interrupt-cells = <1>; interrupt-controller; }; }; cpu_1: cpu@1 { compatible = "spacemit,x100", "riscv"; device_type = "cpu"; reg = <1>; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", "sha", "shcounterenw", "shgatpa", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smaia", "smstateen", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "ssnpm", "ssstateen", "sstc", "sstvala", "sstvecd", "ssu64xl", "svade", "svinval", "svnapot", "svpbmt", "za64rs", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfbfmin", "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkt", "zvbb", "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <256>; d-cache-block-size = <64>; d-cache-size = <65536>; d-cache-sets = <256>; next-level-cache = <&l2_cache0>; mmu-type = "riscv,sv39"; cpu1_intc: interrupt-controller { compatible = "riscv,cpu-intc"; #interrupt-cells = <1>; interrupt-controller; }; }; cpu_2: cpu@2 { compatible = "spacemit,x100", "riscv"; device_type = "cpu"; reg = <2>; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", "sha", "shcounterenw", "shgatpa", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smaia", "smstateen", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "ssnpm", "ssstateen", "sstc", "sstvala", "sstvecd", "ssu64xl", "svade", "svinval", "svnapot", "svpbmt", "za64rs", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfbfmin", "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkt", "zvbb", "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <256>; d-cache-block-size = <64>; d-cache-size = <65536>; d-cache-sets = <256>; next-level-cache = <&l2_cache0>; mmu-type = "riscv,sv39"; cpu2_intc: interrupt-controller { compatible = "riscv,cpu-intc"; #interrupt-cells = <1>; interrupt-controller; }; }; cpu_3: cpu@3 { compatible = "spacemit,x100", "riscv"; device_type = "cpu"; reg = <3>; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", "sha", "shcounterenw", "shgatpa", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smaia", "smstateen", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "ssnpm", "ssstateen", "sstc", "sstvala", "sstvecd", "ssu64xl", "svade", "svinval", "svnapot", "svpbmt", "za64rs", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfbfmin", "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkt", "zvbb", "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <256>; d-cache-block-size = <64>; d-cache-size = <65536>; d-cache-sets = <256>; next-level-cache = <&l2_cache0>; mmu-type = "riscv,sv39"; cpu3_intc: interrupt-controller { compatible = "riscv,cpu-intc"; #interrupt-cells = <1>; interrupt-controller; }; }; cpu_4: cpu@4 { compatible = "spacemit,x100", "riscv"; device_type = "cpu"; reg = <4>; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", "sha", "shcounterenw", "shgatpa", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smaia", "smstateen", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "ssnpm", "ssstateen", "sstc", "sstvala", "sstvecd", "ssu64xl", "svade", "svinval", "svnapot", "svpbmt", "za64rs", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfbfmin", "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkt", "zvbb", "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <256>; d-cache-block-size = <64>; d-cache-size = <65536>; d-cache-sets = <256>; next-level-cache = <&l2_cache1>; mmu-type = "riscv,sv39"; cpu4_intc: interrupt-controller { compatible = "riscv,cpu-intc"; #interrupt-cells = <1>; interrupt-controller; }; }; cpu_5: cpu@5 { compatible = "spacemit,x100", "riscv"; device_type = "cpu"; reg = <5>; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", "sha", "shcounterenw", "shgatpa", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smaia", "smstateen", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "ssnpm", "ssstateen", "sstc", "sstvala", "sstvecd", "ssu64xl", "svade", "svinval", "svnapot", "svpbmt", "za64rs", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfbfmin", "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkt", "zvbb", "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <256>; d-cache-block-size = <64>; d-cache-size = <65536>; d-cache-sets = <256>; next-level-cache = <&l2_cache1>; mmu-type = "riscv,sv39"; cpu5_intc: interrupt-controller { compatible = "riscv,cpu-intc"; #interrupt-cells = <1>; interrupt-controller; }; }; cpu_6: cpu@6 { compatible = "spacemit,x100", "riscv"; device_type = "cpu"; reg = <6>; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", "sha", "shcounterenw", "shgatpa", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smaia", "smstateen", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "ssnpm", "ssstateen", "sstc", "sstvala", "sstvecd", "ssu64xl", "svade", "svinval", "svnapot", "svpbmt", "za64rs", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfbfmin", "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkt", "zvbb", "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <256>; d-cache-block-size = <64>; d-cache-size = <65536>; d-cache-sets = <256>; next-level-cache = <&l2_cache1>; mmu-type = "riscv,sv39"; cpu6_intc: interrupt-controller { compatible = "riscv,cpu-intc"; #interrupt-cells = <1>; interrupt-controller; }; }; cpu_7: cpu@7 { compatible = "spacemit,x100", "riscv"; device_type = "cpu"; reg = <7>; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", "sha", "shcounterenw", "shgatpa", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smaia", "smstateen", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "ssnpm", "ssstateen", "sstc", "sstvala", "sstvecd", "ssu64xl", "svade", "svinval", "svnapot", "svpbmt", "za64rs", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zcmop", "zfa", "zfbfmin", "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkt", "zvbb", "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; riscv,cbom-block-size = <64>; riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <256>; d-cache-block-size = <64>; d-cache-size = <65536>; d-cache-sets = <256>; next-level-cache = <&l2_cache1>; mmu-type = "riscv,sv39"; cpu7_intc: interrupt-controller { compatible = "riscv,cpu-intc"; #interrupt-cells = <1>; interrupt-controller; }; }; l2_cache0: cache-controller-0 { compatible = "cache"; cache-block-size = <64>; cache-level = <2>; cache-size = <4194304>; cache-sets = <4096>; cache-unified; }; l2_cache1: cache-controller-1 { compatible = "cache"; cache-block-size = <64>; cache-level = <2>; cache-size = <4194304>; cache-sets = <4096>; cache-unified; }; cpu-map { cluster0 { core0 { cpu = <&cpu_0>; }; core1 { cpu = <&cpu_1>; }; core2 { cpu = <&cpu_2>; }; core3 { cpu = <&cpu_3>; }; }; cluster1 { core0 { cpu = <&cpu_4>; }; core1 { cpu = <&cpu_5>; }; core2 { cpu = <&cpu_6>; }; core3 { cpu = <&cpu_7>; }; }; }; }; soc: soc { compatible = "simple-bus"; interrupt-parent = <&saplic>; #address-cells = <2>; #size-cells = <2>; dma-noncoherent; ranges; uart0: serial@d4017000 { compatible = "spacemit,k3-uart", "intel,xscale-uart"; reg = <0x0 0xd4017000 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; clock-frequency = <14700000>; interrupts = <42 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; uart2: serial@d4017100 { compatible = "spacemit,k3-uart", "intel,xscale-uart"; reg = <0x0 0xd4017100 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; clock-frequency = <14700000>; interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; uart3: serial@d4017200 { compatible = "spacemit,k3-uart", "intel,xscale-uart"; reg = <0x0 0xd4017200 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; clock-frequency = <14700000>; interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; uart4: serial@d4017300 { compatible = "spacemit,k3-uart", "intel,xscale-uart"; reg = <0x0 0xd4017300 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; clock-frequency = <14700000>; interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; uart5: serial@d4017400 { compatible = "spacemit,k3-uart", "intel,xscale-uart"; reg = <0x0 0xd4017400 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; clock-frequency = <14700000>; interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; uart6: serial@d4017500 { compatible = "spacemit,k3-uart", "intel,xscale-uart"; reg = <0x0 0xd4017500 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; clock-frequency = <14700000>; interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; uart7: serial@d4017600 { compatible = "spacemit,k3-uart", "intel,xscale-uart"; reg = <0x0 0xd4017600 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; clock-frequency = <14700000>; interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; uart8: serial@d4017700 { compatible = "spacemit,k3-uart", "intel,xscale-uart"; reg = <0x0 0xd4017700 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; clock-frequency = <14700000>; interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; uart9: serial@d4017800 { compatible = "spacemit,k3-uart", "intel,xscale-uart"; reg = <0x0 0xd4017800 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; clock-frequency = <14700000>; interrupts = <51 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; uart10: serial@d401f000 { compatible = "spacemit,k3-uart", "intel,xscale-uart"; reg = <0x0 0xd401f000 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; clock-frequency = <14700000>; interrupts = <281 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; simsic: interrupt-controller@e0400000 { compatible = "spacemit,k3-imsics", "riscv,imsics"; reg = <0x0 0xe0400000 0x0 0x200000>; #interrupt-cells = <0>; #msi-cells = <0>; interrupt-controller; interrupts-extended = <&cpu0_intc 9>, <&cpu1_intc 9>, <&cpu2_intc 9>, <&cpu3_intc 9>, <&cpu4_intc 9>, <&cpu5_intc 9>, <&cpu6_intc 9>, <&cpu7_intc 9>; msi-controller; riscv,guest-index-bits = <6>; riscv,hart-index-bits = <4>; riscv,num-guest-ids = <511>; riscv,num-ids = <511>; }; saplic: interrupt-controller@e0804000 { compatible = "spacemit,k3-aplic", "riscv,aplic"; reg = <0x0 0xe0804000 0x0 0x4000>; #interrupt-cells = <2>; interrupt-controller; msi-parent = <&simsic>; riscv,num-sources = <512>; }; clint: timer@e081c000 { compatible = "spacemit,k3-clint", "sifive,clint0"; reg = <0x0 0xe081c000 0x0 0x4000>; interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, <&cpu1_intc 3>, <&cpu1_intc 7>, <&cpu2_intc 3>, <&cpu2_intc 7>, <&cpu3_intc 3>, <&cpu3_intc 7>, <&cpu4_intc 3>, <&cpu4_intc 7>, <&cpu5_intc 3>, <&cpu5_intc 7>, <&cpu6_intc 3>, <&cpu6_intc 7>, <&cpu7_intc 3>, <&cpu7_intc 7>; }; mimsic: interrupt-controller@f1000000 { compatible = "spacemit,k3-imsics", "riscv,imsics"; reg = <0x0 0xf1000000 0x0 0x10000>; #interrupt-cells = <0>; #msi-cells = <0>; interrupt-controller; interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>, <&cpu2_intc 11>, <&cpu3_intc 11>, <&cpu4_intc 11>, <&cpu5_intc 11>, <&cpu6_intc 11>, <&cpu7_intc 11>; msi-controller; riscv,guest-index-bits = <6>; riscv,hart-index-bits = <4>; riscv,num-guest-ids = <511>; riscv,num-ids = <511>; status = "reserved"; }; maplic: interrupt-controller@f1800000 { compatible = "spacemit,k3-aplic", "riscv,aplic"; reg = <0x0 0xf1800000 0x0 0x4000>; #interrupt-cells = <2>; interrupt-controller; msi-parent = <&mimsic>; riscv,children = <&saplic>; riscv,delegation = <&saplic 1 512>; riscv,num-sources = <512>; status = "reserved"; }; }; };
