Path: blob/master/arch/riscv/boot/dts/thead/th1520.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Copyright (C) 2021 Alibaba Group Holding Limited. * Copyright (C) 2023 Jisheng Zhang <[email protected]> */ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/clock/thead,th1520-clk-ap.h> #include <dt-bindings/power/thead,th1520-power.h> #include <dt-bindings/reset/thead,th1520-reset.h> / { compatible = "thead,th1520"; #address-cells = <2>; #size-cells = <2>; cpus: cpus { #address-cells = <1>; #size-cells = <0>; timebase-frequency = <3000000>; c910_0: cpu@0 { compatible = "thead,c910", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", "zihpm"; reg = <0>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; d-cache-block-size = <64>; d-cache-size = <65536>; d-cache-sets = <512>; next-level-cache = <&l2_cache>; mmu-type = "riscv,sv39"; cpu0_intc: interrupt-controller { compatible = "riscv,cpu-intc"; interrupt-controller; #interrupt-cells = <1>; }; }; c910_1: cpu@1 { compatible = "thead,c910", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", "zihpm"; reg = <1>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; d-cache-block-size = <64>; d-cache-size = <65536>; d-cache-sets = <512>; next-level-cache = <&l2_cache>; mmu-type = "riscv,sv39"; cpu1_intc: interrupt-controller { compatible = "riscv,cpu-intc"; interrupt-controller; #interrupt-cells = <1>; }; }; c910_2: cpu@2 { compatible = "thead,c910", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", "zihpm"; reg = <2>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; d-cache-block-size = <64>; d-cache-size = <65536>; d-cache-sets = <512>; next-level-cache = <&l2_cache>; mmu-type = "riscv,sv39"; cpu2_intc: interrupt-controller { compatible = "riscv,cpu-intc"; interrupt-controller; #interrupt-cells = <1>; }; }; c910_3: cpu@3 { compatible = "thead,c910", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", "zihpm"; reg = <3>; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; d-cache-block-size = <64>; d-cache-size = <65536>; d-cache-sets = <512>; next-level-cache = <&l2_cache>; mmu-type = "riscv,sv39"; cpu3_intc: interrupt-controller { compatible = "riscv,cpu-intc"; interrupt-controller; #interrupt-cells = <1>; }; }; l2_cache: l2-cache { compatible = "cache"; cache-block-size = <64>; cache-level = <2>; cache-size = <1048576>; cache-sets = <1024>; cache-unified; }; }; pmu { compatible = "riscv,pmu"; riscv,event-to-mhpmcounters = <0x00003 0x00003 0x0007fff8>, <0x00004 0x00004 0x0007fff8>, <0x00005 0x00005 0x0007fff8>, <0x00006 0x00006 0x0007fff8>, <0x00007 0x00007 0x0007fff8>, <0x00008 0x00008 0x0007fff8>, <0x00009 0x00009 0x0007fff8>, <0x0000a 0x0000a 0x0007fff8>, <0x10000 0x10000 0x0007fff8>, <0x10001 0x10001 0x0007fff8>, <0x10002 0x10002 0x0007fff8>, <0x10003 0x10003 0x0007fff8>, <0x10010 0x10010 0x0007fff8>, <0x10011 0x10011 0x0007fff8>, <0x10012 0x10012 0x0007fff8>, <0x10013 0x10013 0x0007fff8>; riscv,event-to-mhpmevent = <0x00003 0x00000000 0x00000001>, <0x00004 0x00000000 0x00000002>, <0x00006 0x00000000 0x00000006>, <0x00005 0x00000000 0x00000007>, <0x00007 0x00000000 0x00000008>, <0x00008 0x00000000 0x00000009>, <0x00009 0x00000000 0x0000000a>, <0x0000a 0x00000000 0x0000000b>, <0x10000 0x00000000 0x0000000c>, <0x10001 0x00000000 0x0000000d>, <0x10002 0x00000000 0x0000000e>, <0x10003 0x00000000 0x0000000f>, <0x10010 0x00000000 0x00000010>, <0x10011 0x00000000 0x00000011>, <0x10012 0x00000000 0x00000012>, <0x10013 0x00000000 0x00000013>; riscv,raw-event-to-mhpmcounters = <0x00000000 0x00000001 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x00000002 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x00000003 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x00000004 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x00000005 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x00000006 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x00000007 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x00000008 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x00000009 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x0000000a 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x00000010 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x00000011 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x00000012 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x00000013 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x00000014 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x00000015 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x00000016 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x00000017 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x00000018 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x00000019 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x0000001a 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x0000001b 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x0000001c 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x0000001d 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x0000001e 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x0000001f 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x00000020 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x00000021 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x00000022 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x00000023 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x00000024 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x00000025 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x00000026 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x00000027 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x00000028 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x00000029 0xffffffff 0xffffffff 0x0007fff8>, <0x00000000 0x0000002a 0xffffffff 0xffffffff 0x0007fff8>; }; osc: oscillator { compatible = "fixed-clock"; clock-output-names = "osc_24m"; #clock-cells = <0>; }; osc_32k: 32k-oscillator { compatible = "fixed-clock"; clock-output-names = "osc_32k"; #clock-cells = <0>; }; aonsys_clk: clock-73728000 { compatible = "fixed-clock"; clock-frequency = <73728000>; clock-output-names = "aonsys_clk"; #clock-cells = <0>; }; stmmac_axi_config: stmmac-axi-config { snps,wr_osr_lmt = <15>; snps,rd_osr_lmt = <15>; snps,blen = <0 0 64 32 0 0 0>; }; aon: aon { compatible = "thead,th1520-aon"; mboxes = <&mbox_910t 1>; mbox-names = "aon"; resets = <&rst TH1520_RESET_ID_GPU_CLKGEN>; reset-names = "gpu-clkgen"; #power-domain-cells = <1>; }; soc { compatible = "simple-bus"; interrupt-parent = <&plic>; #address-cells = <2>; #size-cells = <2>; dma-noncoherent; ranges; plic: interrupt-controller@ffd8000000 { compatible = "thead,th1520-plic", "thead,c900-plic"; reg = <0xff 0xd8000000 0x0 0x01000000>; interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, <&cpu1_intc 11>, <&cpu1_intc 9>, <&cpu2_intc 11>, <&cpu2_intc 9>, <&cpu3_intc 11>, <&cpu3_intc 9>; interrupt-controller; #address-cells = <0>; #interrupt-cells = <2>; riscv,ndev = <240>; }; clint: timer@ffdc000000 { compatible = "thead,th1520-clint", "thead,c900-clint"; reg = <0xff 0xdc000000 0x0 0x00010000>; interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, <&cpu1_intc 3>, <&cpu1_intc 7>, <&cpu2_intc 3>, <&cpu2_intc 7>, <&cpu3_intc 3>, <&cpu3_intc 7>; }; spi0: spi@ffe700c000 { compatible = "thead,th1520-spi", "snps,dw-apb-ssi"; reg = <0xff 0xe700c000 0x0 0x1000>; interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk CLK_SPI>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; uart0: serial@ffe7014000 { compatible = "snps,dw-apb-uart"; reg = <0xff 0xe7014000 0x0 0x100>; interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART0_PCLK>; clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; }; gmac1: ethernet@ffe7060000 { compatible = "thead,th1520-gmac", "snps,dwmac-3.70a"; reg = <0xff 0xe7060000 0x0 0x2000>, <0xff 0xec004000 0x0 0x1000>; reg-names = "dwmac", "apb"; interrupts = <67 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC1>, <&clk CLK_PERISYS_APB4_HCLK>; clock-names = "stmmaceth", "pclk", "apb"; snps,pbl = <32>; snps,fixed-burst; snps,multicast-filter-bins = <64>; snps,perfect-filter-entries = <32>; snps,axi-config = <&stmmac_axi_config>; status = "disabled"; mdio1: mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; }; }; gmac0: ethernet@ffe7070000 { compatible = "thead,th1520-gmac", "snps,dwmac-3.70a"; reg = <0xff 0xe7070000 0x0 0x2000>, <0xff 0xec003000 0x0 0x1000>; reg-names = "dwmac", "apb"; interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC0>, <&clk CLK_PERISYS_APB4_HCLK>; clock-names = "stmmaceth", "pclk", "apb"; snps,pbl = <32>; snps,fixed-burst; snps,multicast-filter-bins = <64>; snps,perfect-filter-entries = <32>; snps,axi-config = <&stmmac_axi_config>; status = "disabled"; mdio0: mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; }; }; emmc: mmc@ffe7080000 { compatible = "thead,th1520-dwcmshc"; reg = <0xff 0xe7080000 0x0 0x10000>; interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk CLK_EMMC_SDIO>; clock-names = "core"; status = "disabled"; }; sdio0: mmc@ffe7090000 { compatible = "thead,th1520-dwcmshc"; reg = <0xff 0xe7090000 0x0 0x10000>; interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk CLK_EMMC_SDIO>; clock-names = "core"; status = "disabled"; }; sdio1: mmc@ffe70a0000 { compatible = "thead,th1520-dwcmshc"; reg = <0xff 0xe70a0000 0x0 0x10000>; interrupts = <71 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk CLK_EMMC_SDIO>; clock-names = "core"; status = "disabled"; }; uart1: serial@ffe7f00000 { compatible = "snps,dw-apb-uart"; reg = <0xff 0xe7f00000 0x0 0x100>; interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART1_PCLK>; clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; }; uart3: serial@ffe7f04000 { compatible = "snps,dw-apb-uart"; reg = <0xff 0xe7f04000 0x0 0x100>; interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART3_PCLK>; clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; }; gpio@ffe7f34000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xe7f34000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk CLK_GPIO2>; clock-names = "bus"; gpio2: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; ngpios = <32>; gpio-ranges = <&padctrl0_apsys 0 0 32>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; }; }; gpio@ffe7f38000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xe7f38000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk CLK_GPIO3>; clock-names = "bus"; gpio3: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; ngpios = <23>; gpio-ranges = <&padctrl0_apsys 0 32 23>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; }; }; padctrl1_apsys: pinctrl@ffe7f3c000 { compatible = "thead,th1520-pinctrl"; reg = <0xff 0xe7f3c000 0x0 0x1000>; clocks = <&clk CLK_PADCTRL1>; thead,pad-group = <2>; }; gpio@ffec005000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xec005000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk CLK_GPIO0>; clock-names = "bus"; gpio0: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; ngpios = <32>; gpio-ranges = <&padctrl1_apsys 0 0 32>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; }; }; gpio@ffec006000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xec006000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk CLK_GPIO1>; clock-names = "bus"; gpio1: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; ngpios = <31>; gpio-ranges = <&padctrl1_apsys 0 32 31>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; }; }; padctrl0_apsys: pinctrl@ffec007000 { compatible = "thead,th1520-pinctrl"; reg = <0xff 0xec007000 0x0 0x1000>; clocks = <&clk CLK_PADCTRL0>; thead,pad-group = <3>; }; uart2: serial@ffec010000 { compatible = "snps,dw-apb-uart"; reg = <0xff 0xec010000 0x0 0x4000>; interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART2_PCLK>; clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; }; clk: clock-controller@ffef010000 { compatible = "thead,th1520-clk-ap"; reg = <0xff 0xef010000 0x0 0x1000>; clocks = <&osc>; #clock-cells = <1>; }; rst: reset-controller@ffef528000 { compatible = "thead,th1520-reset"; reg = <0xff 0xef528000 0x0 0x4f>; #reset-cells = <1>; }; clk_vo: clock-controller@ffef528050 { compatible = "thead,th1520-clk-vo"; reg = <0xff 0xef528050 0x0 0xfb0>; clocks = <&clk CLK_VIDEO_PLL>; #clock-cells = <1>; }; dmac0: dma-controller@ffefc00000 { compatible = "snps,axi-dma-1.01a"; reg = <0xff 0xefc00000 0x0 0x1000>; interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk CLK_PERI_APB_PCLK>, <&clk CLK_PERI_APB_PCLK>; clock-names = "core-clk", "cfgr-clk"; #dma-cells = <1>; dma-channels = <4>; snps,block-size = <65536 65536 65536 65536>; snps,priority = <0 1 2 3>; snps,dma-masters = <1>; snps,data-width = <4>; snps,axi-max-burst-len = <16>; status = "disabled"; }; timer0: timer@ffefc32000 { compatible = "snps,dw-apb-timer"; reg = <0xff 0xefc32000 0x0 0x14>; clocks = <&clk CLK_PERI_APB_PCLK>; clock-names = "timer"; interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; timer1: timer@ffefc32014 { compatible = "snps,dw-apb-timer"; reg = <0xff 0xefc32014 0x0 0x14>; clocks = <&clk CLK_PERI_APB_PCLK>; clock-names = "timer"; interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; timer2: timer@ffefc32028 { compatible = "snps,dw-apb-timer"; reg = <0xff 0xefc32028 0x0 0x14>; clocks = <&clk CLK_PERI_APB_PCLK>; clock-names = "timer"; interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; timer3: timer@ffefc3203c { compatible = "snps,dw-apb-timer"; reg = <0xff 0xefc3203c 0x0 0x14>; clocks = <&clk CLK_PERI_APB_PCLK>; clock-names = "timer"; interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; uart4: serial@fff7f08000 { compatible = "snps,dw-apb-uart"; reg = <0xff 0xf7f08000 0x0 0x4000>; interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART4_PCLK>; clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; }; uart5: serial@fff7f0c000 { compatible = "snps,dw-apb-uart"; reg = <0xff 0xf7f0c000 0x0 0x4000>; interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART5_PCLK>; clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; }; timer4: timer@ffffc33000 { compatible = "snps,dw-apb-timer"; reg = <0xff 0xffc33000 0x0 0x14>; clocks = <&clk CLK_PERI_APB_PCLK>; clock-names = "timer"; interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; timer5: timer@ffffc33014 { compatible = "snps,dw-apb-timer"; reg = <0xff 0xffc33014 0x0 0x14>; clocks = <&clk CLK_PERI_APB_PCLK>; clock-names = "timer"; interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; timer6: timer@ffffc33028 { compatible = "snps,dw-apb-timer"; reg = <0xff 0xffc33028 0x0 0x14>; clocks = <&clk CLK_PERI_APB_PCLK>; clock-names = "timer"; interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; timer7: timer@ffffc3303c { compatible = "snps,dw-apb-timer"; reg = <0xff 0xffc3303c 0x0 0x14>; clocks = <&clk CLK_PERI_APB_PCLK>; clock-names = "timer"; interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; mbox_910t: mailbox@ffffc38000 { compatible = "thead,th1520-mbox"; reg = <0xff 0xffc38000 0x0 0x6000>, <0xff 0xffc40000 0x0 0x6000>, <0xff 0xffc4c000 0x0 0x2000>, <0xff 0xffc54000 0x0 0x2000>; reg-names = "local", "remote-icu0", "remote-icu1", "remote-icu2"; clocks = <&clk CLK_MBOX0>, <&clk CLK_MBOX1>, <&clk CLK_MBOX2>, <&clk CLK_MBOX3>; clock-names = "clk-local", "clk-remote-icu0", "clk-remote-icu1", "clk-remote-icu2"; interrupt-parent = <&plic>; interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; #mbox-cells = <1>; }; gpio@fffff41000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xfff41000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; aogpio: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; ngpios = <16>; gpio-ranges = <&padctrl_aosys 0 9 16>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; interrupts = <76 IRQ_TYPE_LEVEL_HIGH>; }; }; padctrl_aosys: pinctrl@fffff4a000 { compatible = "thead,th1520-pinctrl"; reg = <0xff 0xfff4a000 0x0 0x2000>; clocks = <&aonsys_clk>; thead,pad-group = <1>; }; pvt: pvt@fffff4e000 { compatible = "moortec,mr75203"; reg = <0xff 0xfff4e000 0x0 0x80>, <0xff 0xfff4e080 0x0 0x100>, <0xff 0xfff4e180 0x0 0x680>, <0xff 0xfff4e800 0x0 0x600>; reg-names = "common", "ts", "pd", "vm"; clocks = <&aonsys_clk>; #thermal-sensor-cells = <1>; }; gpio@fffff52000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xfff52000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; gpio4: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; ngpios = <23>; gpio-ranges = <&padctrl_aosys 0 25 22>, <&padctrl_aosys 22 7 1>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; }; }; }; };