Path: blob/master/arch/riscv/crypto/aes-riscv64-zvkned-zvkb.S
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/* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */1//2// This file is dual-licensed, meaning that you can use it under your3// choice of either of the following two licenses:4//5// Copyright 2023 The OpenSSL Project Authors. All Rights Reserved.6//7// Licensed under the Apache License 2.0 (the "License"). You can obtain8// a copy in the file LICENSE in the source distribution or at9// https://www.openssl.org/source/license.html10//11// or12//13// Copyright (c) 2023, Jerry Shih <jerry.shih@sifive.com>14// Copyright 2024 Google LLC15// All rights reserved.16//17// Redistribution and use in source and binary forms, with or without18// modification, are permitted provided that the following conditions19// are met:20// 1. Redistributions of source code must retain the above copyright21// notice, this list of conditions and the following disclaimer.22// 2. Redistributions in binary form must reproduce the above copyright23// notice, this list of conditions and the following disclaimer in the24// documentation and/or other materials provided with the distribution.25//26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.3738// The generated code of this file depends on the following RISC-V extensions:39// - RV64I40// - RISC-V Vector ('V') with VLEN >= 12841// - RISC-V Vector AES block cipher extension ('Zvkned')42// - RISC-V Vector Cryptography Bit-manipulation extension ('Zvkb')4344#include <linux/linkage.h>4546.text47.option arch, +zvkned, +zvkb4849#include "aes-macros.S"5051#define KEYP a052#define INP a153#define OUTP a254#define LEN a355#define IVP a45657#define LEN32 a558#define VL_E32 a659#define VL_BLOCKS a76061.macro aes_ctr32_crypt keylen62// LEN32 = number of blocks, rounded up, in 32-bit words.63addi t0, LEN, 1564srli t0, t0, 465slli LEN32, t0, 26667// Create a mask that selects the last 32-bit word of each 128-bit68// block. This is the word that contains the (big-endian) counter.69li t0, 0x8870vsetvli t1, zero, e8, m1, ta, ma71vmv.v.x v0, t07273// Load the IV into v31. The last 32-bit word contains the counter.74vsetivli zero, 4, e32, m1, ta, ma75vle32.v v31, (IVP)7677// Convert the big-endian counter into little-endian.78vsetivli zero, 4, e32, m1, ta, mu79vrev8.v v31, v31, v0.t8081// Splat the IV to v16 (with LMUL=4). The number of copies is the82// maximum number of blocks that will be processed per iteration.83vsetvli zero, LEN32, e32, m4, ta, ma84vmv.v.i v16, 085vaesz.vs v16, v318687// v20 = [x, x, x, 0, x, x, x, 1, ...]88viota.m v20, v0, v0.t89// v16 = [IV0, IV1, IV2, counter+0, IV0, IV1, IV2, counter+1, ...]90vsetvli VL_E32, LEN32, e32, m4, ta, mu91vadd.vv v16, v16, v20, v0.t9293j 2f941:95// Set the number of blocks to process in this iteration. vl=VL_E32 is96// the length in 32-bit words, i.e. 4 times the number of blocks.97vsetvli VL_E32, LEN32, e32, m4, ta, mu9899// Increment the counters by the number of blocks processed in the100// previous iteration.101vadd.vx v16, v16, VL_BLOCKS, v0.t1022:103// Prepare the AES inputs into v24.104vmv.v.v v24, v16105vrev8.v v24, v24, v0.t // Convert counters back to big-endian.106107// Encrypt the AES inputs to create the next portion of the keystream.108aes_encrypt v24, \keylen109110// XOR the data with the keystream.111vsetvli t0, LEN, e8, m4, ta, ma112vle8.v v20, (INP)113vxor.vv v20, v20, v24114vse8.v v20, (OUTP)115116// Advance the pointers and update the remaining length.117add INP, INP, t0118add OUTP, OUTP, t0119sub LEN, LEN, t0120sub LEN32, LEN32, VL_E32121srli VL_BLOCKS, VL_E32, 2122123// Repeat if more data remains.124bnez LEN, 1b125126// Update *IVP to contain the next counter.127vsetivli zero, 4, e32, m1, ta, mu128vadd.vx v16, v16, VL_BLOCKS, v0.t129vrev8.v v16, v16, v0.t // Convert counters back to big-endian.130vse32.v v16, (IVP)131132ret133.endm134135// void aes_ctr32_crypt_zvkned_zvkb(const struct crypto_aes_ctx *key,136// const u8 *in, u8 *out, size_t len,137// u8 iv[16]);138SYM_FUNC_START(aes_ctr32_crypt_zvkned_zvkb)139aes_begin KEYP, 128f, 192f140aes_ctr32_crypt 256141128:142aes_ctr32_crypt 128143192:144aes_ctr32_crypt 192145SYM_FUNC_END(aes_ctr32_crypt_zvkned_zvkb)146147148