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torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/arch/riscv/include/asm/checksum.h
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/* SPDX-License-Identifier: GPL-2.0 */

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/*

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 * Checksum routines

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 *

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 * Copyright (C) 2023 Rivos Inc.

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 */

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#ifndef __ASM_RISCV_CHECKSUM_H

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#define __ASM_RISCV_CHECKSUM_H

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#include <linux/in6.h>

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#include <linux/uaccess.h>

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#define ip_fast_csum ip_fast_csum

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extern unsigned int do_csum(const unsigned char *buff, int len);

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#define do_csum do_csum

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/* Default version is sufficient for 32 bit */

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#ifndef CONFIG_32BIT

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#define _HAVE_ARCH_IPV6_CSUM

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__sum16 csum_ipv6_magic(const struct in6_addr *saddr,

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			const struct in6_addr *daddr,

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			__u32 len, __u8 proto, __wsum sum);

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#endif

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/* Define riscv versions of functions before importing asm-generic/checksum.h */

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#include <asm-generic/checksum.h>

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/**

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 * Quickly compute an IP checksum with the assumption that IPv4 headers will

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 * always be in multiples of 32-bits, and have an ihl of at least 5.

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 *

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 * @ihl: the number of 32 bit segments and must be greater than or equal to 5.

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 * @iph: assumed to be word aligned given that NET_IP_ALIGN is set to 2 on

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 *  riscv, defining IP headers to be aligned.

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 */

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static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)

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{

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	unsigned long csum = 0;

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	int pos = 0;

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	do {

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		csum += ((const unsigned int *)iph)[pos];

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		if (IS_ENABLED(CONFIG_32BIT))

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			csum += csum < ((const unsigned int *)iph)[pos];

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	} while (++pos < ihl);

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	/*

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	 * ZBB only saves three instructions on 32-bit and five on 64-bit so not

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	 * worth checking if supported without Alternatives.

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	 */

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	if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB)) {

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		unsigned long fold_temp;

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		asm goto(ALTERNATIVE("j %l[no_zbb]", "nop", 0,

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					      RISCV_ISA_EXT_ZBB, 1)

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		    :

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		    :

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		    :

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		    : no_zbb);

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		if (IS_ENABLED(CONFIG_32BIT)) {

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			asm(".option push				\n\

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			.option arch,+zbb				\n\

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				not	%[fold_temp], %[csum]		\n\

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				rori	%[csum], %[csum], 16		\n\

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				sub	%[csum], %[fold_temp], %[csum]	\n\

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			.option pop"

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			: [csum] "+r" (csum), [fold_temp] "=&r" (fold_temp));

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		} else {

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			asm(".option push				\n\

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			.option arch,+zbb				\n\

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				rori	%[fold_temp], %[csum], 32	\n\

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				add	%[csum], %[fold_temp], %[csum]	\n\

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				srli	%[csum], %[csum], 32		\n\

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				not	%[fold_temp], %[csum]		\n\

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				roriw	%[csum], %[csum], 16		\n\

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				subw	%[csum], %[fold_temp], %[csum]	\n\

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			.option pop"

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			: [csum] "+r" (csum), [fold_temp] "=&r" (fold_temp));

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		}

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		return (__force __sum16)(csum >> 16);

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	}

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no_zbb:

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#ifndef CONFIG_32BIT

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	csum += ror64(csum, 32);

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	csum >>= 32;

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#endif

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	return csum_fold((__force __wsum)csum);

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}

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#endif /* __ASM_RISCV_CHECKSUM_H */

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