Path: blob/master/arch/riscv/include/asm/entry-common.h
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/* SPDX-License-Identifier: GPL-2.0 */12#ifndef _ASM_RISCV_ENTRY_COMMON_H3#define _ASM_RISCV_ENTRY_COMMON_H45#include <asm/stacktrace.h>6#include <asm/thread_info.h>7#include <asm/vector.h>89static inline void arch_exit_to_user_mode_prepare(struct pt_regs *regs,10unsigned long ti_work)11{12if (ti_work & _TIF_RISCV_V_DEFER_RESTORE) {13clear_thread_flag(TIF_RISCV_V_DEFER_RESTORE);14/*15* We are already called with irq disabled, so go without16* keeping track of riscv_v_flags.17*/18riscv_v_vstate_restore(¤t->thread.vstate, regs);19}20}2122#define arch_exit_to_user_mode_prepare arch_exit_to_user_mode_prepare2324void handle_page_fault(struct pt_regs *regs);25void handle_break(struct pt_regs *regs);2627#ifdef CONFIG_RISCV_MISALIGNED28int handle_misaligned_load(struct pt_regs *regs);29int handle_misaligned_store(struct pt_regs *regs);30#else31static inline int handle_misaligned_load(struct pt_regs *regs)32{33return -1;34}3536static inline int handle_misaligned_store(struct pt_regs *regs)37{38return -1;39}40#endif4142#endif /* _ASM_RISCV_ENTRY_COMMON_H */434445