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torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/arch/riscv/include/uapi/asm/auxvec.h
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/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */

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/*

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 * Copyright (C) 2012 ARM Ltd.

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 * Copyright (C) 2015 Regents of the University of California

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 */

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#ifndef _UAPI_ASM_RISCV_AUXVEC_H

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#define _UAPI_ASM_RISCV_AUXVEC_H

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/* vDSO location */

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#define AT_SYSINFO_EHDR 33

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/*

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 * The set of entries below represent more extensive information

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 * about the caches, in the form of two entry per cache type,

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 * one entry containing the cache size in bytes, and the other

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 * containing the cache line size in bytes in the bottom 16 bits

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 * and the cache associativity in the next 16 bits.

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 *

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 * The associativity is such that if N is the 16-bit value, the

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 * cache is N way set associative. A value if 0xffff means fully

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 * associative, a value of 1 means directly mapped.

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 *

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 * For all these fields, a value of 0 means that the information

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 * is not known.

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 */

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#define AT_L1I_CACHESIZE	40

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#define AT_L1I_CACHEGEOMETRY	41

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#define AT_L1D_CACHESIZE	42

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#define AT_L1D_CACHEGEOMETRY	43

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#define AT_L2_CACHESIZE		44

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#define AT_L2_CACHEGEOMETRY	45

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#define AT_L3_CACHESIZE		46

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#define AT_L3_CACHEGEOMETRY	47

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/* entries in ARCH_DLINFO */

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#define AT_VECTOR_SIZE_ARCH	10

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#define AT_MINSIGSTKSZ		51

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#endif /* _UAPI_ASM_RISCV_AUXVEC_H */

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