Path: blob/master/arch/sh/boards/mach-kfr2r09/lcd_wqvga.c
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// SPDX-License-Identifier: GPL-2.01/*2* KFR2R09 LCD panel support3*4* Copyright (C) 2009 Magnus Damm5*6* Register settings based on the out-of-tree t33fb.c driver7* Copyright (C) 2008 Lineo Solutions, Inc.8*/910#include <linux/delay.h>11#include <linux/err.h>12#include <linux/fb.h>13#include <linux/init.h>14#include <linux/kernel.h>15#include <linux/module.h>16#include <linux/gpio.h>17#include <video/sh_mobile_lcdc.h>18#include <mach/kfr2r09.h>19#include <cpu/sh7724.h>2021/* The on-board LCD module is a Hitachi TX07D34VM0AAA. This module is made22* up of a 240x400 LCD hooked up to a R61517 driver IC. The driver IC is23* communicating with the main port of the LCDC using an 18-bit SYS interface.24*25* The device code for this LCD module is 0x01221517.26*/2728static const unsigned char data_frame_if[] = {290x02, /* WEMODE: 1=cont, 0=one-shot */300x00, 0x00,310x00, /* EPF, DFM */320x02, /* RIM[1] : 1 (18bpp) */33};3435static const unsigned char data_panel[] = {360x0b,370x63, /* 400 lines */380x04, 0x00, 0x00, 0x04, 0x11, 0x00, 0x00,39};4041static const unsigned char data_timing[] = {420x00, 0x00, 0x13, 0x08, 0x08,43};4445static const unsigned char data_timing_src[] = {460x11, 0x01, 0x00, 0x01,47};4849static const unsigned char data_gamma[] = {500x01, 0x02, 0x08, 0x23, 0x03, 0x0c, 0x00, 0x06, 0x00, 0x00,510x01, 0x00, 0x0c, 0x23, 0x03, 0x08, 0x02, 0x06, 0x00, 0x00,52};5354static const unsigned char data_power[] = {550x07, 0xc5, 0xdc, 0x02, 0x33, 0x0a,56};5758static unsigned long read_reg(void *sohandle,59struct sh_mobile_lcdc_sys_bus_ops *so)60{61return so->read_data(sohandle);62}6364static void write_reg(void *sohandle,65struct sh_mobile_lcdc_sys_bus_ops *so,66int i, unsigned long v)67{68if (i)69so->write_data(sohandle, v); /* PTH4/LCDRS High [param, 17:0] */70else71so->write_index(sohandle, v); /* PTH4/LCDRS Low [cmd, 7:0] */72}7374static void write_data(void *sohandle,75struct sh_mobile_lcdc_sys_bus_ops *so,76unsigned char const *data, int no_data)77{78int i;7980for (i = 0; i < no_data; i++)81write_reg(sohandle, so, 1, data[i]);82}8384static unsigned long read_device_code(void *sohandle,85struct sh_mobile_lcdc_sys_bus_ops *so)86{87unsigned long device_code;8889/* access protect OFF */90write_reg(sohandle, so, 0, 0xb0);91write_reg(sohandle, so, 1, 0x00);9293/* deep standby OFF */94write_reg(sohandle, so, 0, 0xb1);95write_reg(sohandle, so, 1, 0x00);9697/* device code command */98write_reg(sohandle, so, 0, 0xbf);99mdelay(50);100101/* dummy read */102read_reg(sohandle, so);103104/* read device code */105device_code = ((read_reg(sohandle, so) & 0xff) << 24);106device_code |= ((read_reg(sohandle, so) & 0xff) << 16);107device_code |= ((read_reg(sohandle, so) & 0xff) << 8);108device_code |= (read_reg(sohandle, so) & 0xff);109110return device_code;111}112113static void write_memory_start(void *sohandle,114struct sh_mobile_lcdc_sys_bus_ops *so)115{116write_reg(sohandle, so, 0, 0x2c);117}118119static void clear_memory(void *sohandle,120struct sh_mobile_lcdc_sys_bus_ops *so)121{122int i;123124/* write start */125write_memory_start(sohandle, so);126127/* paint it black */128for (i = 0; i < (240 * 400); i++)129write_reg(sohandle, so, 1, 0x00);130}131132static void display_on(void *sohandle,133struct sh_mobile_lcdc_sys_bus_ops *so)134{135/* access protect off */136write_reg(sohandle, so, 0, 0xb0);137write_reg(sohandle, so, 1, 0x00);138139/* exit deep standby mode */140write_reg(sohandle, so, 0, 0xb1);141write_reg(sohandle, so, 1, 0x00);142143/* frame memory I/F */144write_reg(sohandle, so, 0, 0xb3);145write_data(sohandle, so, data_frame_if, ARRAY_SIZE(data_frame_if));146147/* display mode and frame memory write mode */148write_reg(sohandle, so, 0, 0xb4);149write_reg(sohandle, so, 1, 0x00); /* DBI, internal clock */150151/* panel */152write_reg(sohandle, so, 0, 0xc0);153write_data(sohandle, so, data_panel, ARRAY_SIZE(data_panel));154155/* timing (normal) */156write_reg(sohandle, so, 0, 0xc1);157write_data(sohandle, so, data_timing, ARRAY_SIZE(data_timing));158159/* timing (partial) */160write_reg(sohandle, so, 0, 0xc2);161write_data(sohandle, so, data_timing, ARRAY_SIZE(data_timing));162163/* timing (idle) */164write_reg(sohandle, so, 0, 0xc3);165write_data(sohandle, so, data_timing, ARRAY_SIZE(data_timing));166167/* timing (source/VCOM/gate driving) */168write_reg(sohandle, so, 0, 0xc4);169write_data(sohandle, so, data_timing_src, ARRAY_SIZE(data_timing_src));170171/* gamma (red) */172write_reg(sohandle, so, 0, 0xc8);173write_data(sohandle, so, data_gamma, ARRAY_SIZE(data_gamma));174175/* gamma (green) */176write_reg(sohandle, so, 0, 0xc9);177write_data(sohandle, so, data_gamma, ARRAY_SIZE(data_gamma));178179/* gamma (blue) */180write_reg(sohandle, so, 0, 0xca);181write_data(sohandle, so, data_gamma, ARRAY_SIZE(data_gamma));182183/* power (common) */184write_reg(sohandle, so, 0, 0xd0);185write_data(sohandle, so, data_power, ARRAY_SIZE(data_power));186187/* VCOM */188write_reg(sohandle, so, 0, 0xd1);189write_reg(sohandle, so, 1, 0x00);190write_reg(sohandle, so, 1, 0x0f);191write_reg(sohandle, so, 1, 0x02);192193/* power (normal) */194write_reg(sohandle, so, 0, 0xd2);195write_reg(sohandle, so, 1, 0x63);196write_reg(sohandle, so, 1, 0x24);197198/* power (partial) */199write_reg(sohandle, so, 0, 0xd3);200write_reg(sohandle, so, 1, 0x63);201write_reg(sohandle, so, 1, 0x24);202203/* power (idle) */204write_reg(sohandle, so, 0, 0xd4);205write_reg(sohandle, so, 1, 0x63);206write_reg(sohandle, so, 1, 0x24);207208write_reg(sohandle, so, 0, 0xd8);209write_reg(sohandle, so, 1, 0x77);210write_reg(sohandle, so, 1, 0x77);211212/* TE signal */213write_reg(sohandle, so, 0, 0x35);214write_reg(sohandle, so, 1, 0x00);215216/* TE signal line */217write_reg(sohandle, so, 0, 0x44);218write_reg(sohandle, so, 1, 0x00);219write_reg(sohandle, so, 1, 0x00);220221/* column address */222write_reg(sohandle, so, 0, 0x2a);223write_reg(sohandle, so, 1, 0x00);224write_reg(sohandle, so, 1, 0x00);225write_reg(sohandle, so, 1, 0x00);226write_reg(sohandle, so, 1, 0xef);227228/* page address */229write_reg(sohandle, so, 0, 0x2b);230write_reg(sohandle, so, 1, 0x00);231write_reg(sohandle, so, 1, 0x00);232write_reg(sohandle, so, 1, 0x01);233write_reg(sohandle, so, 1, 0x8f);234235/* exit sleep mode */236write_reg(sohandle, so, 0, 0x11);237238mdelay(120);239240/* clear vram */241clear_memory(sohandle, so);242243/* display ON */244write_reg(sohandle, so, 0, 0x29);245mdelay(1);246247write_memory_start(sohandle, so);248}249250int kfr2r09_lcd_setup(void *sohandle, struct sh_mobile_lcdc_sys_bus_ops *so)251{252/* power on */253gpio_set_value(GPIO_PTF4, 0); /* PROTECT/ -> L */254gpio_set_value(GPIO_PTE4, 0); /* LCD_RST/ -> L */255gpio_set_value(GPIO_PTF4, 1); /* PROTECT/ -> H */256udelay(1100);257gpio_set_value(GPIO_PTE4, 1); /* LCD_RST/ -> H */258udelay(10);259gpio_set_value(GPIO_PTF4, 0); /* PROTECT/ -> L */260mdelay(20);261262if (read_device_code(sohandle, so) != 0x01221517)263return -ENODEV;264265pr_info("KFR2R09 WQVGA LCD Module detected.\n");266267display_on(sohandle, so);268return 0;269}270271void kfr2r09_lcd_start(void *sohandle, struct sh_mobile_lcdc_sys_bus_ops *so)272{273write_memory_start(sohandle, so);274}275276277