Path: blob/master/arch/sh/boards/mach-sh7763rdp/setup.c
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// SPDX-License-Identifier: GPL-2.01/*2* linux/arch/sh/boards/renesas/sh7763rdp/setup.c3*4* Renesas Solutions sh7763rdp board5*6* Copyright (C) 2008 Renesas Solutions Corp.7* Copyright (C) 2008 Nobuhiro Iwamatsu <[email protected]>8*/9#include <linux/init.h>10#include <linux/platform_device.h>11#include <linux/interrupt.h>12#include <linux/input.h>13#include <linux/mtd/physmap.h>14#include <linux/fb.h>15#include <linux/io.h>16#include <linux/sh_eth.h>17#include <linux/sh_intc.h>18#include <mach/sh7763rdp.h>19#include <asm/sh7760fb.h>2021/* NOR Flash */22static struct mtd_partition sh7763rdp_nor_flash_partitions[] = {23{24.name = "U-Boot",25.offset = 0,26.size = (2 * 128 * 1024),27.mask_flags = MTD_WRITEABLE, /* Read-only */28}, {29.name = "Linux-Kernel",30.offset = MTDPART_OFS_APPEND,31.size = (20 * 128 * 1024),32}, {33.name = "Root Filesystem",34.offset = MTDPART_OFS_APPEND,35.size = MTDPART_SIZ_FULL,36},37};3839static struct physmap_flash_data sh7763rdp_nor_flash_data = {40.width = 2,41.parts = sh7763rdp_nor_flash_partitions,42.nr_parts = ARRAY_SIZE(sh7763rdp_nor_flash_partitions),43};4445static struct resource sh7763rdp_nor_flash_resources[] = {46[0] = {47.name = "NOR Flash",48.start = 0,49.end = (64 * 1024 * 1024),50.flags = IORESOURCE_MEM,51},52};5354static struct platform_device sh7763rdp_nor_flash_device = {55.name = "physmap-flash",56.resource = sh7763rdp_nor_flash_resources,57.num_resources = ARRAY_SIZE(sh7763rdp_nor_flash_resources),58.dev = {59.platform_data = &sh7763rdp_nor_flash_data,60},61};6263/*64* SH-Ether65*66* SH Ether of SH7763 has multi IRQ handling.67* (0x920,0x940,0x960 -> 0x920)68*/69static struct resource sh_eth_resources[] = {70{71.start = 0xFEE00800, /* use eth1 */72.end = 0xFEE00F7C - 1,73.flags = IORESOURCE_MEM,74}, {75.start = 0xFEE01800, /* TSU */76.end = 0xFEE01FFF,77.flags = IORESOURCE_MEM,78}, {79.start = evt2irq(0x920), /* irq number */80.flags = IORESOURCE_IRQ,81},82};8384static struct sh_eth_plat_data sh7763_eth_pdata = {85.phy = 1,86.phy_interface = PHY_INTERFACE_MODE_MII,87};8889static struct platform_device sh7763rdp_eth_device = {90.name = "sh7763-gether",91.resource = sh_eth_resources,92.num_resources = ARRAY_SIZE(sh_eth_resources),93.dev = {94.platform_data = &sh7763_eth_pdata,95},96};9798/* SH7763 LCDC */99static struct resource sh7763rdp_fb_resources[] = {100{101.start = 0xFFE80000,102.end = 0xFFE80442 - 1,103.flags = IORESOURCE_MEM,104},105};106107static struct fb_videomode sh7763fb_videomode = {108.refresh = 60,109.name = "VGA Monitor",110.xres = 640,111.yres = 480,112.pixclock = 10000,113.left_margin = 80,114.right_margin = 24,115.upper_margin = 30,116.lower_margin = 1,117.hsync_len = 96,118.vsync_len = 1,119.sync = 0,120.vmode = FB_VMODE_NONINTERLACED,121.flag = FB_MODE_IS_UNKNOWN,122};123124static struct sh7760fb_platdata sh7763fb_def_pdata = {125.def_mode = &sh7763fb_videomode,126.ldmtr = (LDMTR_TFT_COLOR_16|LDMTR_MCNT),127.lddfr = LDDFR_16BPP_RGB565,128.ldpmmr = 0x0000,129.ldpspr = 0xFFFF,130.ldaclnr = 0x0001,131.ldickr = 0x1102,132.rotate = 0,133.novsync = 0,134.blank = NULL,135};136137static struct platform_device sh7763rdp_fb_device = {138.name = "sh7760-lcdc",139.resource = sh7763rdp_fb_resources,140.num_resources = ARRAY_SIZE(sh7763rdp_fb_resources),141.dev = {142.platform_data = &sh7763fb_def_pdata,143},144};145146static struct platform_device *sh7763rdp_devices[] __initdata = {147&sh7763rdp_nor_flash_device,148&sh7763rdp_eth_device,149&sh7763rdp_fb_device,150};151152static int __init sh7763rdp_devices_setup(void)153{154return platform_add_devices(sh7763rdp_devices,155ARRAY_SIZE(sh7763rdp_devices));156}157device_initcall(sh7763rdp_devices_setup);158159static void __init sh7763rdp_setup(char **cmdline_p)160{161/* Board version check */162if (__raw_readw(CPLD_BOARD_ID_ERV_REG) == 0xECB1)163printk(KERN_INFO "RTE Standard Configuration\n");164else165printk(KERN_INFO "RTA Standard Configuration\n");166167/* USB pin select bits (clear bit 5-2 to 0) */168__raw_writew((__raw_readw(PORT_PSEL2) & 0xFFC3), PORT_PSEL2);169/* USBH setup port I controls to other (clear bits 4-9 to 0) */170__raw_writew(__raw_readw(PORT_PICR) & 0xFC0F, PORT_PICR);171172/* Select USB Host controller */173__raw_writew(0x00, USB_USBHSC);174175/* For LCD */176/* set PTJ7-1, bits 15-2 of PJCR to 0 */177__raw_writew(__raw_readw(PORT_PJCR) & 0x0003, PORT_PJCR);178/* set PTI5, bits 11-10 of PICR to 0 */179__raw_writew(__raw_readw(PORT_PICR) & 0xF3FF, PORT_PICR);180__raw_writew(0, PORT_PKCR);181__raw_writew(0, PORT_PLCR);182/* set PSEL2 bits 14-8, 5-4, of PSEL2 to 0 */183__raw_writew((__raw_readw(PORT_PSEL2) & 0x00C0), PORT_PSEL2);184/* set PSEL3 bits 14-12, 6-4, 2-0 of PSEL3 to 0 */185__raw_writew((__raw_readw(PORT_PSEL3) & 0x0700), PORT_PSEL3);186187/* For HAC */188/* bit3-0 0100:HAC & SSI1 enable */189__raw_writew((__raw_readw(PORT_PSEL1) & 0xFFF0) | 0x0004, PORT_PSEL1);190/* bit14 1:SSI_HAC_CLK enable */191__raw_writew(__raw_readw(PORT_PSEL4) | 0x4000, PORT_PSEL4);192193/* SH-Ether */194__raw_writew((__raw_readw(PORT_PSEL1) & ~0xff00) | 0x2400, PORT_PSEL1);195__raw_writew(0x0, PORT_PFCR);196__raw_writew(0x0, PORT_PFCR);197__raw_writew(0x0, PORT_PFCR);198199/* MMC */200/*selects SCIF and MMC other functions */201__raw_writew(0x0001, PORT_PSEL0);202/* MMC clock operates */203__raw_writel(__raw_readl(MSTPCR1) & ~0x8, MSTPCR1);204__raw_writew(__raw_readw(PORT_PACR) & ~0x3000, PORT_PACR);205__raw_writew(__raw_readw(PORT_PCCR) & ~0xCFC3, PORT_PCCR);206}207208static struct sh_machine_vector mv_sh7763rdp __initmv = {209.mv_name = "sh7763drp",210.mv_setup = sh7763rdp_setup,211.mv_init_irq = init_sh7763rdp_IRQ,212};213214215