/* SPDX-License-Identifier: GPL-2.01*2* Low-Level PCI Support for SH7780 targets3*4* Dustin McIntire ([email protected]) (c) 20015* Paul Mundt ([email protected]) (c) 20036*/78#ifndef _PCI_SH7780_H_9#define _PCI_SH7780_H_1011/* SH7780 Control Registers */12#define PCIECR 0xFE00000813#define PCIECR_ENBL 0x011415/* SH7780 Specific Values */16#define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */17#define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */1819#define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */2021/* SH7780 PCI Config Registers */22#define SH7780_PCIIR 0x114 /* PCI Interrupt Register */23#define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */24#define SH7780_PCIAIR 0x11C /* Error Address Register */25#define SH7780_PCICIR 0x120 /* Error Command/Data Register */26#define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */27#define SH7780_PCIAINTM 0x134 /* Arbiter Int. Mask Register */28#define SH7780_PCIBMIR 0x138 /* Error Bus Master Register */29#define SH7780_PCIPAR 0x1C0 /* PIO Address Register */30#define SH7780_PCIPINT 0x1CC /* Power Mgmnt Int. Register */31#define SH7780_PCIPINTM 0x1D0 /* Power Mgmnt Mask Register */3233#define SH7780_PCIMBR(x) (0x1E0 + ((x) * 8))34#define SH7780_PCIMBMR(x) (0x1E4 + ((x) * 8))35#define SH7780_PCIIOBR 0x1F836#define SH7780_PCIIOBMR 0x1FC37#define SH7780_PCICSCR0 0x210 /* Cache Snoop1 Cnt. Register */38#define SH7780_PCICSCR1 0x214 /* Cache Snoop2 Cnt. Register */39#define SH7780_PCICSAR0 0x218 /* Cache Snoop1 Addr. Register */40#define SH7780_PCICSAR1 0x21C /* Cache Snoop2 Addr. Register */4142#endif /* _PCI_SH7780_H_ */434445