/* SPDX-License-Identifier: GPL-2.01*2* Common header for the legacy SH DMA driver and the new dmaengine driver3*4* extracted from arch/sh/include/asm/dma-sh.h:5*6* Copyright (C) 2000 Takashi YOSHII7* Copyright (C) 2003 Paul Mundt8*/9#ifndef DMA_REGISTER_H10#define DMA_REGISTER_H1112/* DMA registers */13#define SAR 0x00 /* Source Address Register */14#define DAR 0x04 /* Destination Address Register */15#define TCR 0x08 /* Transfer Count Register */16#define CHCR 0x0C /* Channel Control Register */17#define DMAOR 0x40 /* DMA Operation Register */1819/* DMAOR definitions */20#define DMAOR_AE 0x00000004 /* Address Error Flag */21#define DMAOR_NMIF 0x0000000222#define DMAOR_DME 0x00000001 /* DMA Master Enable */2324/* Definitions for the SuperH DMAC */25#define REQ_L 0x0000000026#define REQ_E 0x0008000027#define RACK_H 0x0000000028#define RACK_L 0x0004000029#define ACK_R 0x0000000030#define ACK_W 0x0002000031#define ACK_H 0x0000000032#define ACK_L 0x0001000033#define DM_INC 0x00004000 /* Destination addresses are incremented */34#define DM_DEC 0x00008000 /* Destination addresses are decremented */35#define DM_FIX 0x0000c000 /* Destination address is fixed */36#define SM_INC 0x00001000 /* Source addresses are incremented */37#define SM_DEC 0x00002000 /* Source addresses are decremented */38#define SM_FIX 0x00003000 /* Source address is fixed */39#define RS_IN 0x0000020040#define RS_OUT 0x0000030041#define RS_AUTO 0x00000400 /* Auto Request */42#define RS_ERS 0x00000800 /* DMA extended resource selector */43#define TS_BLK 0x0000004044#define TM_BUR 0x0000002045#define CHCR_DE 0x00000001 /* DMA Enable */46#define CHCR_TE 0x00000002 /* Transfer End Flag */47#define CHCR_IE 0x00000004 /* Interrupt Enable */4849#endif505152