/* SPDX-License-Identifier: GPL-2.01*2* include/asm-sh/cpu-sh2/cache.h3*4* Copyright (C) 2003 Paul Mundt5*/6#ifndef __ASM_CPU_SH2_CACHE_H7#define __ASM_CPU_SH2_CACHE_H89#define L1_CACHE_SHIFT 41011#define SH_CACHE_VALID 112#define SH_CACHE_UPDATED 213#define SH_CACHE_COMBINED 414#define SH_CACHE_ASSOC 81516#if defined(CONFIG_CPU_SUBTYPE_SH7619)17#define SH_CCR 0xffffffec1819#define CCR_CACHE_CE 0x01 /* Cache enable */20#define CCR_CACHE_WT 0x02 /* CCR[bit1=1,bit2=1] */21/* 0x00000000-0x7fffffff: Write-through */22/* 0x80000000-0x9fffffff: Write-back */23/* 0xc0000000-0xdfffffff: Write-through */24#define CCR_CACHE_CB 0x04 /* CCR[bit1=0,bit2=0] */25/* 0x00000000-0x7fffffff: Write-back */26/* 0x80000000-0x9fffffff: Write-through */27/* 0xc0000000-0xdfffffff: Write-back */28#define CCR_CACHE_CF 0x08 /* Cache invalidate */2930#define CACHE_OC_ADDRESS_ARRAY 0xf000000031#define CACHE_OC_DATA_ARRAY 0xf10000003233#define CCR_CACHE_ENABLE CCR_CACHE_CE34#define CCR_CACHE_INVALIDATE CCR_CACHE_CF35#define CACHE_PHYSADDR_MASK 0x1ffffc003637#endif3839#endif /* __ASM_CPU_SH2_CACHE_H */404142