Path: blob/master/arch/sh/kernel/cpu/sh3/serial-sh7720.c
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// SPDX-License-Identifier: GPL-2.01#include <linux/serial_sci.h>2#include <linux/serial_core.h>3#include <linux/io.h>4#include <cpu/serial.h>5#include <cpu/gpio.h>67static void sh7720_sci_init_pins(struct uart_port *port, unsigned int cflag)8{9unsigned short data;1011if (cflag & CRTSCTS) {12/* enable RTS/CTS */13if (port->mapbase == 0xa4430000) { /* SCIF0 */14/* Clear PTCR bit 9-2; enable all scif pins but sck */15data = __raw_readw(PORT_PTCR);16__raw_writew((data & 0xfc03), PORT_PTCR);17} else if (port->mapbase == 0xa4438000) { /* SCIF1 */18/* Clear PVCR bit 9-2 */19data = __raw_readw(PORT_PVCR);20__raw_writew((data & 0xfc03), PORT_PVCR);21}22} else {23if (port->mapbase == 0xa4430000) { /* SCIF0 */24/* Clear PTCR bit 5-2; enable only tx and rx */25data = __raw_readw(PORT_PTCR);26__raw_writew((data & 0xffc3), PORT_PTCR);27} else if (port->mapbase == 0xa4438000) { /* SCIF1 */28/* Clear PVCR bit 5-2 */29data = __raw_readw(PORT_PVCR);30__raw_writew((data & 0xffc3), PORT_PVCR);31}32}33}3435struct plat_sci_port_ops sh7720_sci_port_ops = {36.init_pins = sh7720_sci_init_pins,37};383940