Path: blob/master/arch/sh/kernel/cpu/sh3/setup-sh770x.c
26495 views
// SPDX-License-Identifier: GPL-2.01/*2* SH3 Setup code for SH7706, SH7707, SH7708, SH77093*4* Copyright (C) 2007 Magnus Damm5* Copyright (C) 2009 Paul Mundt6*7* Based on setup-sh7709.c8*9* Copyright (C) 2006 Paul Mundt10*/11#include <linux/init.h>12#include <linux/io.h>13#include <linux/irq.h>14#include <linux/platform_device.h>15#include <linux/serial.h>16#include <linux/serial_sci.h>17#include <linux/sh_timer.h>18#include <linux/sh_intc.h>19#include <cpu/serial.h>20#include <asm/platform_early.h>2122enum {23UNUSED = 0,2425/* interrupt sources */26IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,27PINT07, PINT815,28DMAC, SCIF0, SCIF2, SCI, ADC_ADI,29LCDC, PCC0, PCC1,30TMU0, TMU1, TMU2,31RTC, WDT, REF,32};3334static struct intc_vect vectors[] __initdata = {35INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),36INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),37INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),38INTC_VECT(RTC, 0x4c0),39INTC_VECT(SCI, 0x4e0), INTC_VECT(SCI, 0x500),40INTC_VECT(SCI, 0x520), INTC_VECT(SCI, 0x540),41INTC_VECT(WDT, 0x560),42INTC_VECT(REF, 0x580),43INTC_VECT(REF, 0x5a0),44#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \45defined(CONFIG_CPU_SUBTYPE_SH7707) || \46defined(CONFIG_CPU_SUBTYPE_SH7709)47/* IRQ0->5 are handled in setup-sh3.c */48INTC_VECT(DMAC, 0x800), INTC_VECT(DMAC, 0x820),49INTC_VECT(DMAC, 0x840), INTC_VECT(DMAC, 0x860),50INTC_VECT(ADC_ADI, 0x980),51INTC_VECT(SCIF2, 0x900), INTC_VECT(SCIF2, 0x920),52INTC_VECT(SCIF2, 0x940), INTC_VECT(SCIF2, 0x960),53#endif54#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \55defined(CONFIG_CPU_SUBTYPE_SH7709)56INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),57INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),58INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0),59#endif60#if defined(CONFIG_CPU_SUBTYPE_SH7707)61INTC_VECT(LCDC, 0x9a0),62INTC_VECT(PCC0, 0x9c0), INTC_VECT(PCC1, 0x9e0),63#endif64};6566static struct intc_prio_reg prio_registers[] __initdata = {67{ 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },68{ 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } },69#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \70defined(CONFIG_CPU_SUBTYPE_SH7707) || \71defined(CONFIG_CPU_SUBTYPE_SH7709)72{ 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },73{ 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },74{ 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC, 0, SCIF2, ADC_ADI } },75#endif76#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \77defined(CONFIG_CPU_SUBTYPE_SH7709)78{ 0xa4000018, 0, 16, 4, /* IPRD */ { PINT07, PINT815, } },79{ 0xa400001a, 0, 16, 4, /* IPRE */ { 0, SCIF0 } },80#endif81#if defined(CONFIG_CPU_SUBTYPE_SH7707)82{ 0xa400001c, 0, 16, 4, /* IPRF */ { 0, LCDC, PCC0, PCC1, } },83#endif84};8586static DECLARE_INTC_DESC(intc_desc, "sh770x", vectors, NULL,87NULL, prio_registers, NULL);8889static struct resource rtc_resources[] = {90[0] = {91.start = 0xfffffec0,92.end = 0xfffffec0 + 0x1e,93.flags = IORESOURCE_IO,94},95[1] = {96.start = evt2irq(0x480),97.flags = IORESOURCE_IRQ,98},99};100101static struct platform_device rtc_device = {102.name = "sh-rtc",103.id = -1,104.num_resources = ARRAY_SIZE(rtc_resources),105.resource = rtc_resources,106};107108static struct plat_sci_port scif0_platform_data = {109.type = PORT_SCI,110.ops = &sh770x_sci_port_ops,111};112113static struct resource scif0_resources[] = {114DEFINE_RES_MEM(0xfffffe80, 0x10),115DEFINE_RES_IRQ(evt2irq(0x4e0)),116};117118static struct platform_device scif0_device = {119.name = "sh-sci",120.id = 0,121.resource = scif0_resources,122.num_resources = ARRAY_SIZE(scif0_resources),123.dev = {124.platform_data = &scif0_platform_data,125},126};127#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \128defined(CONFIG_CPU_SUBTYPE_SH7707) || \129defined(CONFIG_CPU_SUBTYPE_SH7709)130static struct plat_sci_port scif1_platform_data = {131.type = PORT_SCIF,132.ops = &sh770x_sci_port_ops,133.regtype = SCIx_SH3_SCIF_REGTYPE,134};135136static struct resource scif1_resources[] = {137DEFINE_RES_MEM(0xa4000150, 0x10),138DEFINE_RES_IRQ(evt2irq(0x900)),139};140141static struct platform_device scif1_device = {142.name = "sh-sci",143.id = 1,144.resource = scif1_resources,145.num_resources = ARRAY_SIZE(scif1_resources),146.dev = {147.platform_data = &scif1_platform_data,148},149};150#endif151#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \152defined(CONFIG_CPU_SUBTYPE_SH7709)153static struct plat_sci_port scif2_platform_data = {154.type = PORT_IRDA,155.ops = &sh770x_sci_port_ops,156};157158static struct resource scif2_resources[] = {159DEFINE_RES_MEM(0xa4000140, 0x10),160DEFINE_RES_IRQ(evt2irq(0x880)),161};162163static struct platform_device scif2_device = {164.name = "sh-sci",165.id = 2,166.resource = scif2_resources,167.num_resources = ARRAY_SIZE(scif2_resources),168.dev = {169.platform_data = &scif2_platform_data,170},171};172#endif173174static struct sh_timer_config tmu0_platform_data = {175.channels_mask = 7,176};177178static struct resource tmu0_resources[] = {179DEFINE_RES_MEM(0xfffffe90, 0x2c),180DEFINE_RES_IRQ(evt2irq(0x400)),181DEFINE_RES_IRQ(evt2irq(0x420)),182DEFINE_RES_IRQ(evt2irq(0x440)),183};184185static struct platform_device tmu0_device = {186.name = "sh-tmu-sh3",187.id = 0,188.dev = {189.platform_data = &tmu0_platform_data,190},191.resource = tmu0_resources,192.num_resources = ARRAY_SIZE(tmu0_resources),193};194195static struct platform_device *sh770x_devices[] __initdata = {196&scif0_device,197#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \198defined(CONFIG_CPU_SUBTYPE_SH7707) || \199defined(CONFIG_CPU_SUBTYPE_SH7709)200&scif1_device,201#endif202#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \203defined(CONFIG_CPU_SUBTYPE_SH7709)204&scif2_device,205#endif206&tmu0_device,207&rtc_device,208};209210static int __init sh770x_devices_setup(void)211{212return platform_add_devices(sh770x_devices,213ARRAY_SIZE(sh770x_devices));214}215arch_initcall(sh770x_devices_setup);216217static struct platform_device *sh770x_early_devices[] __initdata = {218&scif0_device,219#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \220defined(CONFIG_CPU_SUBTYPE_SH7707) || \221defined(CONFIG_CPU_SUBTYPE_SH7709)222&scif1_device,223#endif224#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \225defined(CONFIG_CPU_SUBTYPE_SH7709)226&scif2_device,227#endif228&tmu0_device,229};230231void __init plat_early_device_setup(void)232{233sh_early_platform_add_devices(sh770x_early_devices,234ARRAY_SIZE(sh770x_early_devices));235}236237void __init plat_irq_setup(void)238{239register_intc_controller(&intc_desc);240#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \241defined(CONFIG_CPU_SUBTYPE_SH7707) || \242defined(CONFIG_CPU_SUBTYPE_SH7709)243plat_irq_setup_sh3();244#endif245}246247248