CoCalc -- clock-sh7734.c

GitHub Repository: torvalds/linux
Path: blob/master/arch/sh/kernel/cpu/sh4a/clock-sh7734.c
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// SPDX-License-Identifier: GPL-2.0
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/*
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 * arch/sh/kernel/cpu/sh4a/clock-sh7734.c
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 *
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 * Clock framework for SH7734
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 *
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 * Copyright (C) 2011, 2012 Nobuhiro Iwamatsu <[email protected]>
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 * Copyright (C) 2011, 2012 Renesas Solutions Corp.
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 */
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/clkdev.h>
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#include <linux/delay.h>
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#include <asm/clock.h>
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#include <asm/freq.h>
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static struct clk extal_clk = {
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	.rate       = 33333333,
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};
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#define MODEMR          (0xFFCC0020)
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#define MODEMR_MASK     (0x6)
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#define MODEMR_533MHZ   (0x2)
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static unsigned long pll_recalc(struct clk *clk)
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{
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	int mode = 12;
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	u32 r = __raw_readl(MODEMR);
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	if ((r & MODEMR_MASK) & MODEMR_533MHZ)
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		mode = 16;
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	return clk->parent->rate * mode;
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}
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static struct sh_clk_ops pll_clk_ops = {
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	.recalc		= pll_recalc,
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};
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static struct clk pll_clk = {
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	.ops        = &pll_clk_ops,
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	.parent     = &extal_clk,
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	.flags      = CLK_ENABLE_ON_INIT,
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};
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static struct clk *main_clks[] = {
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	&extal_clk,
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	&pll_clk,
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};
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static int multipliers[] = { 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
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static int divisors[] = { 1, 3, 2, 3, 4, 6, 8, 9, 12, 16, 18, 24 };
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static struct clk_div_mult_table div4_div_mult_table = {
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	.divisors = divisors,
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	.nr_divisors = ARRAY_SIZE(divisors),
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	.multipliers = multipliers,
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	.nr_multipliers = ARRAY_SIZE(multipliers),
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};
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static struct clk_div4_table div4_table = {
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	.div_mult_table = &div4_div_mult_table,
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};
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enum { DIV4_I, DIV4_S, DIV4_B, DIV4_M, DIV4_S1, DIV4_P, DIV4_NR };
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#define DIV4(_reg, _bit, _mask, _flags) \
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	SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
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struct clk div4_clks[DIV4_NR] = {
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	[DIV4_I] = DIV4(FRQMR1, 28, 0x0003, CLK_ENABLE_ON_INIT),
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	[DIV4_S] = DIV4(FRQMR1, 20, 0x000C, CLK_ENABLE_ON_INIT),
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	[DIV4_B] = DIV4(FRQMR1, 16, 0x0140, CLK_ENABLE_ON_INIT),
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	[DIV4_M] = DIV4(FRQMR1, 12, 0x0004, CLK_ENABLE_ON_INIT),
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	[DIV4_S1] = DIV4(FRQMR1, 4, 0x0030, CLK_ENABLE_ON_INIT),
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	[DIV4_P] = DIV4(FRQMR1, 0, 0x0140, CLK_ENABLE_ON_INIT),
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};
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#define MSTPCR0	0xFFC80030
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#define MSTPCR1	0xFFC80034
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#define MSTPCR3	0xFFC8003C
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enum {
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	MSTP030, MSTP029, /* IIC */
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	MSTP026, MSTP025, MSTP024, /* SCIF */
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	MSTP023,
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	MSTP022, MSTP021,
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	MSTP019, /* HSCIF */
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	MSTP016, MSTP015, MSTP014, /* TMU / TIMER */
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	MSTP012, MSTP011, MSTP010, MSTP009, MSTP008, /* SSI */
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	MSTP007, /* HSPI */
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	MSTP115, /* ADMAC */
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	MSTP114, /* GETHER */
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	MSTP111, /* DMAC */
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	MSTP109, /* VIDEOIN1 */
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	MSTP108, /* VIDEOIN0 */
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	MSTP107, /* RGPVBG */
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	MSTP106, /* 2DG */
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	MSTP103, /* VIEW */
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	MSTP100, /* USB */
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	MSTP331, /* MMC */
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	MSTP330, /* MIMLB */
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	MSTP323, /* SDHI0 */
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	MSTP322, /* SDHI1 */
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	MSTP321, /* SDHI2 */
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	MSTP320, /* RQSPI */
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	MSTP319, /* SRC0 */
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	MSTP318, /* SRC1 */
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	MSTP317, /* RSPI */
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	MSTP316, /* RCAN0 */
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	MSTP315, /* RCAN1 */
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	MSTP314, /* FLTCL */
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	MSTP313, /* ADC */
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	MSTP312, /* MTU */
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	MSTP304, /* IE-BUS */
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	MSTP303, /* RTC */
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	MSTP302, /* HIF */
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	MSTP301, /* STIF0 */
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	MSTP300, /* STIF1 */
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	MSTP_NR };
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static struct clk mstp_clks[MSTP_NR] = {
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	/* MSTPCR0 */
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	[MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0),
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	[MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
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	[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
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	[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
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	[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
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	[MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
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	[MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
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	[MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
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	[MSTP019] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
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	[MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
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	[MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
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	[MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0),
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	[MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0),
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	[MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
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	[MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
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	[MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
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	[MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
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	[MSTP007] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
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	/* MSTPCR1 */
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	[MSTP115] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 15, 0),
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	[MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0),
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	[MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0),
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	[MSTP109] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
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	[MSTP108] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 8, 0),
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	[MSTP107] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 7, 0),
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	[MSTP106] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 6, 0),
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	[MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0),
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	[MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 0, 0),
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	/* MSTPCR3 */
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	[MSTP331] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 31, 0),
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	[MSTP330] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 30, 0),
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	[MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 23, 0),
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	[MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0),
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	[MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0),
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	[MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0),
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	[MSTP319] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 19, 0),
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	[MSTP318] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 18, 0),
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	[MSTP317] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 17, 0),
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	[MSTP316] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 16, 0),
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	[MSTP315] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 15, 0),
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	[MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 14, 0),
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	[MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 13, 0),
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	[MSTP312] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 12, 0),
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	[MSTP304] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3,  4, 0),
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	[MSTP303] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3,  3, 0),
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	[MSTP302] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3,  2, 0),
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	[MSTP301] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3,  1, 0),
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	[MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3,  0, 0),
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};
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static struct clk_lookup lookups[] = {
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	/* main clocks */
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	CLKDEV_CON_ID("extal", &extal_clk),
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	CLKDEV_CON_ID("pll_clk", &pll_clk),
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	/* clocks */
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	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
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	CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_S]),
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	CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_M]),
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	CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
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	CLKDEV_CON_ID("shyway_clk1", &div4_clks[DIV4_S1]),
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	CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
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	/* MSTP32 clocks */
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	CLKDEV_DEV_ID("i2c-sh7734.0", &mstp_clks[MSTP030]),
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	CLKDEV_DEV_ID("i2c-sh7734.1", &mstp_clks[MSTP029]),
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	CLKDEV_ICK_ID("fck", "sh-sci.0", &mstp_clks[MSTP026]),
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	CLKDEV_ICK_ID("fck", "sh-sci.1", &mstp_clks[MSTP025]),
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	CLKDEV_ICK_ID("fck", "sh-sci.2", &mstp_clks[MSTP024]),
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	CLKDEV_ICK_ID("fck", "sh-sci.3", &mstp_clks[MSTP023]),
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	CLKDEV_ICK_ID("fck", "sh-sci.4", &mstp_clks[MSTP022]),
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	CLKDEV_ICK_ID("fck", "sh-sci.5", &mstp_clks[MSTP021]),
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	CLKDEV_CON_ID("hscif", &mstp_clks[MSTP019]),
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	CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP016]),
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	CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP015]),
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	CLKDEV_ICK_ID("fck", "sh-tmu.2", &mstp_clks[MSTP014]),
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	CLKDEV_CON_ID("ssi0", &mstp_clks[MSTP012]),
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	CLKDEV_CON_ID("ssi1", &mstp_clks[MSTP011]),
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	CLKDEV_CON_ID("ssi2", &mstp_clks[MSTP010]),
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	CLKDEV_CON_ID("ssi3", &mstp_clks[MSTP009]),
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	CLKDEV_CON_ID("sss", &mstp_clks[MSTP008]),
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	CLKDEV_CON_ID("hspi", &mstp_clks[MSTP007]),
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	CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP100]),
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	CLKDEV_CON_ID("videoin0", &mstp_clks[MSTP109]),
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	CLKDEV_CON_ID("videoin1", &mstp_clks[MSTP108]),
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	CLKDEV_CON_ID("rgpvg", &mstp_clks[MSTP107]),
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	CLKDEV_CON_ID("2dg", &mstp_clks[MSTP106]),
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	CLKDEV_CON_ID("view", &mstp_clks[MSTP103]),
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	CLKDEV_CON_ID("mmc0", &mstp_clks[MSTP331]),
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	CLKDEV_CON_ID("mimlb0", &mstp_clks[MSTP330]),
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	CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP323]),
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	CLKDEV_CON_ID("sdhi1", &mstp_clks[MSTP322]),
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	CLKDEV_CON_ID("sdhi2", &mstp_clks[MSTP321]),
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	CLKDEV_CON_ID("rqspi0", &mstp_clks[MSTP320]),
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	CLKDEV_CON_ID("src0", &mstp_clks[MSTP319]),
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	CLKDEV_CON_ID("src1", &mstp_clks[MSTP318]),
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	CLKDEV_CON_ID("rsp0", &mstp_clks[MSTP317]),
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	CLKDEV_CON_ID("rcan0", &mstp_clks[MSTP316]),
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	CLKDEV_CON_ID("rcan1", &mstp_clks[MSTP315]),
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	CLKDEV_CON_ID("fltcl0", &mstp_clks[MSTP314]),
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	CLKDEV_CON_ID("adc0", &mstp_clks[MSTP313]),
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	CLKDEV_CON_ID("mtu0", &mstp_clks[MSTP312]),
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	CLKDEV_CON_ID("iebus0", &mstp_clks[MSTP304]),
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	CLKDEV_DEV_ID("sh7734-gether.0", &mstp_clks[MSTP114]),
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	CLKDEV_CON_ID("rtc0", &mstp_clks[MSTP303]),
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	CLKDEV_CON_ID("hif0", &mstp_clks[MSTP302]),
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	CLKDEV_CON_ID("stif0", &mstp_clks[MSTP301]),
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	CLKDEV_CON_ID("stif1", &mstp_clks[MSTP300]),
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};
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int __init arch_clk_init(void)
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{
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	int i, ret = 0;
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	for (i = 0; i < ARRAY_SIZE(main_clks); i++)
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		ret |= clk_register(main_clks[i]);
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	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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	if (!ret)
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		ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
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			&div4_table);
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	if (!ret)
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		ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
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	return ret;
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}
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