Path: blob/master/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
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// SPDX-License-Identifier: GPL-2.01/*2* arch/sh/kernel/cpu/sh4a/clock-sh7763.c3*4* SH7763 support for the clock framework5*6* Copyright (C) 2005 Paul Mundt7* Copyright (C) 2007 Yoshihiro Shimoda8*/9#include <linux/init.h>10#include <linux/kernel.h>11#include <linux/io.h>12#include <linux/clkdev.h>13#include <asm/clock.h>14#include <asm/freq.h>15#include <asm/io.h>1617static int bfc_divisors[] = { 1, 1, 1, 8, 1, 1, 1, 1 };18static int p0fc_divisors[] = { 1, 1, 1, 8, 1, 1, 1, 1 };19static int cfc_divisors[] = { 1, 1, 4, 1, 1, 1, 1, 1 };2021static void master_clk_init(struct clk *clk)22{23clk->rate *= p0fc_divisors[(__raw_readl(FRQCR) >> 4) & 0x07];24}2526static struct sh_clk_ops sh7763_master_clk_ops = {27.init = master_clk_init,28};2930static unsigned long module_clk_recalc(struct clk *clk)31{32int idx = ((__raw_readl(FRQCR) >> 4) & 0x07);33return clk->parent->rate / p0fc_divisors[idx];34}3536static struct sh_clk_ops sh7763_module_clk_ops = {37.recalc = module_clk_recalc,38};3940static unsigned long bus_clk_recalc(struct clk *clk)41{42int idx = ((__raw_readl(FRQCR) >> 16) & 0x07);43return clk->parent->rate / bfc_divisors[idx];44}4546static struct sh_clk_ops sh7763_bus_clk_ops = {47.recalc = bus_clk_recalc,48};4950static struct sh_clk_ops sh7763_cpu_clk_ops = {51.recalc = followparent_recalc,52};5354static struct sh_clk_ops *sh7763_clk_ops[] = {55&sh7763_master_clk_ops,56&sh7763_module_clk_ops,57&sh7763_bus_clk_ops,58&sh7763_cpu_clk_ops,59};6061void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)62{63if (idx < ARRAY_SIZE(sh7763_clk_ops))64*ops = sh7763_clk_ops[idx];65}6667static unsigned long shyway_clk_recalc(struct clk *clk)68{69int idx = ((__raw_readl(FRQCR) >> 20) & 0x07);70return clk->parent->rate / cfc_divisors[idx];71}7273static struct sh_clk_ops sh7763_shyway_clk_ops = {74.recalc = shyway_clk_recalc,75};7677static struct clk sh7763_shyway_clk = {78.flags = CLK_ENABLE_ON_INIT,79.ops = &sh7763_shyway_clk_ops,80};8182/*83* Additional SH7763-specific on-chip clocks that aren't already part of the84* clock framework85*/86static struct clk *sh7763_onchip_clocks[] = {87&sh7763_shyway_clk,88};8990static struct clk_lookup lookups[] = {91/* main clocks */92CLKDEV_CON_ID("shyway_clk", &sh7763_shyway_clk),93};9495int __init arch_clk_init(void)96{97struct clk *clk;98int i, ret = 0;99100cpg_clk_init();101102clk = clk_get(NULL, "master_clk");103for (i = 0; i < ARRAY_SIZE(sh7763_onchip_clocks); i++) {104struct clk *clkp = sh7763_onchip_clocks[i];105106clkp->parent = clk;107ret |= clk_register(clkp);108}109110clk_put(clk);111112clkdev_add_table(lookups, ARRAY_SIZE(lookups));113114return ret;115}116117118