CoCalc -- cherrs.S

GitHub Repository: torvalds/linux
Path: blob/master/arch/sparc/kernel/cherrs.S
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/* SPDX-License-Identifier: GPL-2.0 */
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	/* These get patched into the trap table at boot time
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	 * once we know we have a cheetah processor.
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	 */
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	.globl		cheetah_fecc_trap_vector
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	.type		cheetah_fecc_trap_vector,#function
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cheetah_fecc_trap_vector:
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	membar		#Sync
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	ldxa		[%g0] ASI_DCU_CONTROL_REG, %g1
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	andn		%g1, DCU_DC | DCU_IC, %g1
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	stxa		%g1, [%g0] ASI_DCU_CONTROL_REG
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	membar		#Sync
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	sethi		%hi(cheetah_fast_ecc), %g2
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	jmpl		%g2 + %lo(cheetah_fast_ecc), %g0
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	 mov		0, %g1
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	.size		cheetah_fecc_trap_vector,.-cheetah_fecc_trap_vector
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	.globl		cheetah_fecc_trap_vector_tl1
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	.type		cheetah_fecc_trap_vector_tl1,#function
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cheetah_fecc_trap_vector_tl1:
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	membar		#Sync
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	ldxa		[%g0] ASI_DCU_CONTROL_REG, %g1
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	andn		%g1, DCU_DC | DCU_IC, %g1
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	stxa		%g1, [%g0] ASI_DCU_CONTROL_REG
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	membar		#Sync
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	sethi		%hi(cheetah_fast_ecc), %g2
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	jmpl		%g2 + %lo(cheetah_fast_ecc), %g0
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	 mov		1, %g1
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	.size		cheetah_fecc_trap_vector_tl1,.-cheetah_fecc_trap_vector_tl1
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	.globl	cheetah_cee_trap_vector
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	.type	cheetah_cee_trap_vector,#function
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cheetah_cee_trap_vector:
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	membar		#Sync
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	ldxa		[%g0] ASI_DCU_CONTROL_REG, %g1
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	andn		%g1, DCU_IC, %g1
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	stxa		%g1, [%g0] ASI_DCU_CONTROL_REG
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	membar		#Sync
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	sethi		%hi(cheetah_cee), %g2
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	jmpl		%g2 + %lo(cheetah_cee), %g0
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	 mov		0, %g1
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	.size		cheetah_cee_trap_vector,.-cheetah_cee_trap_vector
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	.globl		cheetah_cee_trap_vector_tl1
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	.type		cheetah_cee_trap_vector_tl1,#function
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cheetah_cee_trap_vector_tl1:
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	membar		#Sync
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	ldxa		[%g0] ASI_DCU_CONTROL_REG, %g1
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	andn		%g1, DCU_IC, %g1
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	stxa		%g1, [%g0] ASI_DCU_CONTROL_REG
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	membar		#Sync
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	sethi		%hi(cheetah_cee), %g2
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	jmpl		%g2 + %lo(cheetah_cee), %g0
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	 mov		1, %g1
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	.size		cheetah_cee_trap_vector_tl1,.-cheetah_cee_trap_vector_tl1
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	.globl	cheetah_deferred_trap_vector
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	.type	cheetah_deferred_trap_vector,#function
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cheetah_deferred_trap_vector:
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	membar		#Sync
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	ldxa		[%g0] ASI_DCU_CONTROL_REG, %g1;
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	andn		%g1, DCU_DC | DCU_IC, %g1;
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	stxa		%g1, [%g0] ASI_DCU_CONTROL_REG;
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	membar		#Sync;
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	sethi		%hi(cheetah_deferred_trap), %g2
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	jmpl		%g2 + %lo(cheetah_deferred_trap), %g0
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	 mov		0, %g1
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	.size		cheetah_deferred_trap_vector,.-cheetah_deferred_trap_vector
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	.globl		cheetah_deferred_trap_vector_tl1
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	.type		cheetah_deferred_trap_vector_tl1,#function
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cheetah_deferred_trap_vector_tl1:
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	membar		#Sync;
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	ldxa		[%g0] ASI_DCU_CONTROL_REG, %g1;
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	andn		%g1, DCU_DC | DCU_IC, %g1;
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	stxa		%g1, [%g0] ASI_DCU_CONTROL_REG;
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	membar		#Sync;
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	sethi		%hi(cheetah_deferred_trap), %g2
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	jmpl		%g2 + %lo(cheetah_deferred_trap), %g0
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	 mov		1, %g1
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	.size		cheetah_deferred_trap_vector_tl1,.-cheetah_deferred_trap_vector_tl1
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	/* Cheetah+ specific traps. These are for the new I/D cache parity
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	 * error traps.  The first argument to cheetah_plus_parity_handler
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	 * is encoded as follows:
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	 *
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	 * Bit0:	0=dcache,1=icache
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	 * Bit1:	0=recoverable,1=unrecoverable
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	 */
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	.globl		cheetah_plus_dcpe_trap_vector
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	.type		cheetah_plus_dcpe_trap_vector,#function
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cheetah_plus_dcpe_trap_vector:
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	membar		#Sync
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	sethi		%hi(do_cheetah_plus_data_parity), %g7
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	jmpl		%g7 + %lo(do_cheetah_plus_data_parity), %g0
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	 nop
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	nop
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	nop
99
	nop
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	nop
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	.size		cheetah_plus_dcpe_trap_vector,.-cheetah_plus_dcpe_trap_vector
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	.type		do_cheetah_plus_data_parity,#function
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do_cheetah_plus_data_parity:
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	rdpr		%pil, %g2
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	wrpr		%g0, PIL_NORMAL_MAX, %pil
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	ba,pt		%xcc, etrap_irq
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	 rd		%pc, %g7
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#ifdef CONFIG_TRACE_IRQFLAGS
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	call		trace_hardirqs_off
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	 nop
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#endif
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	mov		0x0, %o0
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	call		cheetah_plus_parity_error
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	 add		%sp, PTREGS_OFF, %o1
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	ba,a,pt		%xcc, rtrap_irq
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	.size		do_cheetah_plus_data_parity,.-do_cheetah_plus_data_parity
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119
	.globl		cheetah_plus_dcpe_trap_vector_tl1
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	.type		cheetah_plus_dcpe_trap_vector_tl1,#function
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cheetah_plus_dcpe_trap_vector_tl1:
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	membar		#Sync
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	wrpr		PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
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	sethi		%hi(do_dcpe_tl1), %g3
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	jmpl		%g3 + %lo(do_dcpe_tl1), %g0
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	 nop
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	nop
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	nop
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	nop
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	.size		cheetah_plus_dcpe_trap_vector_tl1,.-cheetah_plus_dcpe_trap_vector_tl1
131

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	.globl		cheetah_plus_icpe_trap_vector
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	.type		cheetah_plus_icpe_trap_vector,#function
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cheetah_plus_icpe_trap_vector:
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	membar		#Sync
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	sethi		%hi(do_cheetah_plus_insn_parity), %g7
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	jmpl		%g7 + %lo(do_cheetah_plus_insn_parity), %g0
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	 nop
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	nop
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	nop
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	nop
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	nop
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	.size		cheetah_plus_icpe_trap_vector,.-cheetah_plus_icpe_trap_vector
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	.type		do_cheetah_plus_insn_parity,#function
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do_cheetah_plus_insn_parity:
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	rdpr		%pil, %g2
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	wrpr		%g0, PIL_NORMAL_MAX, %pil
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	ba,pt		%xcc, etrap_irq
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	 rd		%pc, %g7
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#ifdef CONFIG_TRACE_IRQFLAGS
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	call		trace_hardirqs_off
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	 nop
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#endif
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	mov		0x1, %o0
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	call		cheetah_plus_parity_error
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	 add		%sp, PTREGS_OFF, %o1
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	ba,a,pt		%xcc, rtrap_irq
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	.size		do_cheetah_plus_insn_parity,.-do_cheetah_plus_insn_parity
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	.globl		cheetah_plus_icpe_trap_vector_tl1
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	.type		cheetah_plus_icpe_trap_vector_tl1,#function
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cheetah_plus_icpe_trap_vector_tl1:
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	membar		#Sync
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	wrpr		PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
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	sethi		%hi(do_icpe_tl1), %g3
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	jmpl		%g3 + %lo(do_icpe_tl1), %g0
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	 nop
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	nop
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	nop
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	nop
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	.size		cheetah_plus_icpe_trap_vector_tl1,.-cheetah_plus_icpe_trap_vector_tl1
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	/* If we take one of these traps when tl >= 1, then we
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	 * jump to interrupt globals.  If some trap level above us
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	 * was also using interrupt globals, we cannot recover.
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	 * We may use all interrupt global registers except %g6.
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	 */
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	.globl		do_dcpe_tl1
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	.type		do_dcpe_tl1,#function
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do_dcpe_tl1:
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	rdpr		%tl, %g1		! Save original trap level
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	mov		1, %g2			! Setup TSTATE checking loop
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	sethi		%hi(TSTATE_IG), %g3	! TSTATE mask bit
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1:	wrpr		%g2, %tl		! Set trap level to check
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	rdpr		%tstate, %g4		! Read TSTATE for this level
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	andcc		%g4, %g3, %g0		! Interrupt globals in use?
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	bne,a,pn	%xcc, do_dcpe_tl1_fatal	! Yep, irrecoverable
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	 wrpr		%g1, %tl		! Restore original trap level
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	add		%g2, 1, %g2		! Next trap level
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	cmp		%g2, %g1		! Hit them all yet?
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	ble,pt		%icc, 1b		! Not yet
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	 nop
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	wrpr		%g1, %tl		! Restore original trap level
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do_dcpe_tl1_nonfatal:	/* Ok we may use interrupt globals safely. */
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	sethi		%hi(dcache_parity_tl1_occurred), %g2
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	lduw		[%g2 + %lo(dcache_parity_tl1_occurred)], %g1
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	add		%g1, 1, %g1
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	stw		%g1, [%g2 + %lo(dcache_parity_tl1_occurred)]
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	/* Reset D-cache parity */
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	sethi		%hi(1 << 16), %g1	! D-cache size
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	mov		(1 << 5), %g2		! D-cache line size
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	sub		%g1, %g2, %g1		! Move down 1 cacheline
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1:	srl		%g1, 14, %g3		! Compute UTAG
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	membar		#Sync
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	stxa		%g3, [%g1] ASI_DCACHE_UTAG
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	membar		#Sync
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	sub		%g2, 8, %g3		! 64-bit data word within line
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2:	membar		#Sync
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	stxa		%g0, [%g1 + %g3] ASI_DCACHE_DATA
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	membar		#Sync
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	subcc		%g3, 8, %g3		! Next 64-bit data word
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	bge,pt		%icc, 2b
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	 nop
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	subcc		%g1, %g2, %g1		! Next cacheline
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	bge,pt		%icc, 1b
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	 nop
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	ba,a,pt		%xcc, dcpe_icpe_tl1_common
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do_dcpe_tl1_fatal:
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	sethi		%hi(1f), %g7
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	ba,pt		%xcc, etraptl1
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1:	or		%g7, %lo(1b), %g7
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	mov		0x2, %o0
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	call		cheetah_plus_parity_error
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	 add		%sp, PTREGS_OFF, %o1
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	ba,a,pt		%xcc, rtrap
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	.size		do_dcpe_tl1,.-do_dcpe_tl1
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	.globl		do_icpe_tl1
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	.type		do_icpe_tl1,#function
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do_icpe_tl1:
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	rdpr		%tl, %g1		! Save original trap level
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	mov		1, %g2			! Setup TSTATE checking loop
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	sethi		%hi(TSTATE_IG), %g3	! TSTATE mask bit
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1:	wrpr		%g2, %tl		! Set trap level to check
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	rdpr		%tstate, %g4		! Read TSTATE for this level
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	andcc		%g4, %g3, %g0		! Interrupt globals in use?
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	bne,a,pn	%xcc, do_icpe_tl1_fatal	! Yep, irrecoverable
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	 wrpr		%g1, %tl		! Restore original trap level
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	add		%g2, 1, %g2		! Next trap level
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	cmp		%g2, %g1		! Hit them all yet?
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	ble,pt		%icc, 1b		! Not yet
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	 nop
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	wrpr		%g1, %tl		! Restore original trap level
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do_icpe_tl1_nonfatal:	/* Ok we may use interrupt globals safely. */
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	sethi		%hi(icache_parity_tl1_occurred), %g2
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	lduw		[%g2 + %lo(icache_parity_tl1_occurred)], %g1
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	add		%g1, 1, %g1
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	stw		%g1, [%g2 + %lo(icache_parity_tl1_occurred)]
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	/* Flush I-cache */
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	sethi		%hi(1 << 15), %g1	! I-cache size
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	mov		(1 << 5), %g2		! I-cache line size
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	sub		%g1, %g2, %g1
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1:	or		%g1, (2 << 3), %g3
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	stxa		%g0, [%g3] ASI_IC_TAG
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	membar		#Sync
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	subcc		%g1, %g2, %g1
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	bge,pt		%icc, 1b
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	 nop
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	ba,a,pt		%xcc, dcpe_icpe_tl1_common
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do_icpe_tl1_fatal:
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	sethi		%hi(1f), %g7
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	ba,pt		%xcc, etraptl1
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1:	or		%g7, %lo(1b), %g7
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	mov		0x3, %o0
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	call		cheetah_plus_parity_error
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	 add		%sp, PTREGS_OFF, %o1
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	ba,a,pt		%xcc, rtrap
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	.size		do_icpe_tl1,.-do_icpe_tl1
272
	
273
	.type		dcpe_icpe_tl1_common,#function
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dcpe_icpe_tl1_common:
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	/* Flush D-cache, re-enable D/I caches in DCU and finally
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	 * retry the trapping instruction.
277
	 */
278
	sethi		%hi(1 << 16), %g1	! D-cache size
279
	mov		(1 << 5), %g2		! D-cache line size
280
	sub		%g1, %g2, %g1
281
1:	stxa		%g0, [%g1] ASI_DCACHE_TAG
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	membar		#Sync
283
	subcc		%g1, %g2, %g1
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	bge,pt		%icc, 1b
285
	 nop
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	ldxa		[%g0] ASI_DCU_CONTROL_REG, %g1
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	or		%g1, (DCU_DC | DCU_IC), %g1
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	stxa		%g1, [%g0] ASI_DCU_CONTROL_REG
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	membar		#Sync
290
	retry
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	.size		dcpe_icpe_tl1_common,.-dcpe_icpe_tl1_common
292

293
	/* Capture I/D/E-cache state into per-cpu error scoreboard.
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	 *
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	 * %g1:		(TL>=0) ? 1 : 0
296
	 * %g2:		scratch
297
	 * %g3:		scratch
298
	 * %g4:		AFSR
299
	 * %g5:		AFAR
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	 * %g6:		unused, will have current thread ptr after etrap
301
	 * %g7:		scratch
302
	 */
303
	.type		__cheetah_log_error,#function
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__cheetah_log_error:
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	/* Put "TL1" software bit into AFSR. */
306
	and		%g1, 0x1, %g1
307
	sllx		%g1, 63, %g2
308
	or		%g4, %g2, %g4
309

310
	/* Get log entry pointer for this cpu at this trap level. */
311
	BRANCH_IF_JALAPENO(g2,g3,50f)
312
	ldxa		[%g0] ASI_SAFARI_CONFIG, %g2
313
	srlx		%g2, 17, %g2
314
	ba,pt		%xcc, 60f
315
	 and		%g2, 0x3ff, %g2
316

317
50:	ldxa		[%g0] ASI_JBUS_CONFIG, %g2
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	srlx		%g2, 17, %g2
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	and		%g2, 0x1f, %g2
320

321
60:	sllx		%g2, 9, %g2
322
	sethi		%hi(cheetah_error_log), %g3
323
	ldx		[%g3 + %lo(cheetah_error_log)], %g3
324
	brz,pn		%g3, 80f
325
	 nop
326

327
	add		%g3, %g2, %g3
328
	sllx		%g1, 8, %g1
329
	add		%g3, %g1, %g1
330

331
	/* %g1 holds pointer to the top of the logging scoreboard */
332
	ldx		[%g1 + 0x0], %g7
333
	cmp		%g7, -1
334
	bne,pn		%xcc, 80f
335
	 nop
336

337
	stx		%g4, [%g1 + 0x0]
338
	stx		%g5, [%g1 + 0x8]
339
	add		%g1, 0x10, %g1
340

341
	/* %g1 now points to D-cache logging area */
342
	set		0x3ff8, %g2	/* DC_addr mask		*/
343
	and		%g5, %g2, %g2	/* DC_addr bits of AFAR	*/
344
	srlx		%g5, 12, %g3
345
	or		%g3, 1, %g3	/* PHYS tag + valid	*/
346

347
10:	ldxa		[%g2] ASI_DCACHE_TAG, %g7
348
	cmp		%g3, %g7	/* TAG match?		*/
349
	bne,pt		%xcc, 13f
350
	 nop
351

352
	/* Yep, what we want, capture state. */
353
	stx		%g2, [%g1 + 0x20]
354
	stx		%g7, [%g1 + 0x28]
355

356
	/* A membar Sync is required before and after utag access. */
357
	membar		#Sync
358
	ldxa		[%g2] ASI_DCACHE_UTAG, %g7
359
	membar		#Sync
360
	stx		%g7, [%g1 + 0x30]
361
	ldxa		[%g2] ASI_DCACHE_SNOOP_TAG, %g7
362
	stx		%g7, [%g1 + 0x38]
363
	clr		%g3
364

365
12:	ldxa		[%g2 + %g3] ASI_DCACHE_DATA, %g7
366
	stx		%g7, [%g1]
367
	add		%g3, (1 << 5), %g3
368
	cmp		%g3, (4 << 5)
369
	bl,pt		%xcc, 12b
370
	 add		%g1, 0x8, %g1
371

372
	ba,pt		%xcc, 20f
373
	 add		%g1, 0x20, %g1
374

375
13:	sethi		%hi(1 << 14), %g7
376
	add		%g2, %g7, %g2
377
	srlx		%g2, 14, %g7
378
	cmp		%g7, 4
379
	bl,pt		%xcc, 10b
380
	 nop
381

382
	add		%g1, 0x40, %g1
383

384
	/* %g1 now points to I-cache logging area */
385
20:	set		0x1fe0, %g2	/* IC_addr mask		*/
386
	and		%g5, %g2, %g2	/* IC_addr bits of AFAR	*/
387
	sllx		%g2, 1, %g2	/* IC_addr[13:6]==VA[12:5] */
388
	srlx		%g5, (13 - 8), %g3 /* Make PTAG */
389
	andn		%g3, 0xff, %g3	/* Mask off undefined bits */
390

391
21:	ldxa		[%g2] ASI_IC_TAG, %g7
392
	andn		%g7, 0xff, %g7
393
	cmp		%g3, %g7
394
	bne,pt		%xcc, 23f
395
	 nop
396

397
	/* Yep, what we want, capture state. */
398
	stx		%g2, [%g1 + 0x40]
399
	stx		%g7, [%g1 + 0x48]
400
	add		%g2, (1 << 3), %g2
401
	ldxa		[%g2] ASI_IC_TAG, %g7
402
	add		%g2, (1 << 3), %g2
403
	stx		%g7, [%g1 + 0x50]
404
	ldxa		[%g2] ASI_IC_TAG, %g7
405
	add		%g2, (1 << 3), %g2
406
	stx		%g7, [%g1 + 0x60]
407
	ldxa		[%g2] ASI_IC_TAG, %g7
408
	stx		%g7, [%g1 + 0x68]
409
	sub		%g2, (3 << 3), %g2
410
	ldxa		[%g2] ASI_IC_STAG, %g7
411
	stx		%g7, [%g1 + 0x58]
412
	clr		%g3
413
	srlx		%g2, 2, %g2
414

415
22:	ldxa		[%g2 + %g3] ASI_IC_INSTR, %g7
416
	stx		%g7, [%g1]
417
	add		%g3, (1 << 3), %g3
418
	cmp		%g3, (8 << 3)
419
	bl,pt		%xcc, 22b
420
	 add		%g1, 0x8, %g1
421

422
	ba,pt		%xcc, 30f
423
	 add		%g1, 0x30, %g1
424

425
23:	sethi		%hi(1 << 14), %g7
426
	add		%g2, %g7, %g2
427
	srlx		%g2, 14, %g7
428
	cmp		%g7, 4
429
	bl,pt		%xcc, 21b
430
	 nop
431

432
	add		%g1, 0x70, %g1
433

434
	/* %g1 now points to E-cache logging area */
435
30:	andn		%g5, (32 - 1), %g2
436
	stx		%g2, [%g1 + 0x20]
437
	ldxa		[%g2] ASI_EC_TAG_DATA, %g7
438
	stx		%g7, [%g1 + 0x28]
439
	ldxa		[%g2] ASI_EC_R, %g0
440
	clr		%g3
441

442
31:	ldxa		[%g3] ASI_EC_DATA, %g7
443
	stx		%g7, [%g1 + %g3]
444
	add		%g3, 0x8, %g3
445
	cmp		%g3, 0x20
446

447
	bl,pt		%xcc, 31b
448
	 nop
449
80:
450
	rdpr		%tt, %g2
451
	cmp		%g2, 0x70
452
	be		c_fast_ecc
453
	 cmp		%g2, 0x63
454
	be		c_cee
455
	 nop
456
	ba,a,pt		%xcc, c_deferred
457
	.size		__cheetah_log_error,.-__cheetah_log_error
458

459
	/* Cheetah FECC trap handling, we get here from tl{0,1}_fecc
460
	 * in the trap table.  That code has done a memory barrier
461
	 * and has disabled both the I-cache and D-cache in the DCU
462
	 * control register.  The I-cache is disabled so that we may
463
	 * capture the corrupted cache line, and the D-cache is disabled
464
	 * because corrupt data may have been placed there and we don't
465
	 * want to reference it.
466
	 *
467
	 * %g1 is one if this trap occurred at %tl >= 1.
468
	 *
469
	 * Next, we turn off error reporting so that we don't recurse.
470
	 */
471
	.globl		cheetah_fast_ecc
472
	.type		cheetah_fast_ecc,#function
473
cheetah_fast_ecc:
474
	ldxa		[%g0] ASI_ESTATE_ERROR_EN, %g2
475
	andn		%g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
476
	stxa		%g2, [%g0] ASI_ESTATE_ERROR_EN
477
	membar		#Sync
478

479
	/* Fetch and clear AFSR/AFAR */
480
	ldxa		[%g0] ASI_AFSR, %g4
481
	ldxa		[%g0] ASI_AFAR, %g5
482
	stxa		%g4, [%g0] ASI_AFSR
483
	membar		#Sync
484

485
	ba,pt		%xcc, __cheetah_log_error
486
	 nop
487
	.size		cheetah_fast_ecc,.-cheetah_fast_ecc
488

489
	.type		c_fast_ecc,#function
490
c_fast_ecc:
491
	rdpr		%pil, %g2
492
	wrpr		%g0, PIL_NORMAL_MAX, %pil
493
	ba,pt		%xcc, etrap_irq
494
	 rd		%pc, %g7
495
#ifdef CONFIG_TRACE_IRQFLAGS
496
	call		trace_hardirqs_off
497
	 nop
498
#endif
499
	mov		%l4, %o1
500
	mov		%l5, %o2
501
	call		cheetah_fecc_handler
502
	 add		%sp, PTREGS_OFF, %o0
503
	ba,a,pt		%xcc, rtrap_irq
504
	.size		c_fast_ecc,.-c_fast_ecc
505

506
	/* Our caller has disabled I-cache and performed membar Sync. */
507
	.globl		cheetah_cee
508
	.type		cheetah_cee,#function
509
cheetah_cee:
510
	ldxa		[%g0] ASI_ESTATE_ERROR_EN, %g2
511
	andn		%g2, ESTATE_ERROR_CEEN, %g2
512
	stxa		%g2, [%g0] ASI_ESTATE_ERROR_EN
513
	membar		#Sync
514

515
	/* Fetch and clear AFSR/AFAR */
516
	ldxa		[%g0] ASI_AFSR, %g4
517
	ldxa		[%g0] ASI_AFAR, %g5
518
	stxa		%g4, [%g0] ASI_AFSR
519
	membar		#Sync
520

521
	ba,pt		%xcc, __cheetah_log_error
522
	 nop
523
	.size		cheetah_cee,.-cheetah_cee
524

525
	.type		c_cee,#function
526
c_cee:
527
	rdpr		%pil, %g2
528
	wrpr		%g0, PIL_NORMAL_MAX, %pil
529
	ba,pt		%xcc, etrap_irq
530
	 rd		%pc, %g7
531
#ifdef CONFIG_TRACE_IRQFLAGS
532
	call		trace_hardirqs_off
533
	 nop
534
#endif
535
	mov		%l4, %o1
536
	mov		%l5, %o2
537
	call		cheetah_cee_handler
538
	 add		%sp, PTREGS_OFF, %o0
539
	ba,a,pt		%xcc, rtrap_irq
540
	.size		c_cee,.-c_cee
541

542
	/* Our caller has disabled I-cache+D-cache and performed membar Sync. */
543
	.globl		cheetah_deferred_trap
544
	.type		cheetah_deferred_trap,#function
545
cheetah_deferred_trap:
546
	ldxa		[%g0] ASI_ESTATE_ERROR_EN, %g2
547
	andn		%g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
548
	stxa		%g2, [%g0] ASI_ESTATE_ERROR_EN
549
	membar		#Sync
550

551
	/* Fetch and clear AFSR/AFAR */
552
	ldxa		[%g0] ASI_AFSR, %g4
553
	ldxa		[%g0] ASI_AFAR, %g5
554
	stxa		%g4, [%g0] ASI_AFSR
555
	membar		#Sync
556

557
	ba,pt		%xcc, __cheetah_log_error
558
	 nop
559
	.size		cheetah_deferred_trap,.-cheetah_deferred_trap
560

561
	.type		c_deferred,#function
562
c_deferred:
563
	rdpr		%pil, %g2
564
	wrpr		%g0, PIL_NORMAL_MAX, %pil
565
	ba,pt		%xcc, etrap_irq
566
	 rd		%pc, %g7
567
#ifdef CONFIG_TRACE_IRQFLAGS
568
	call		trace_hardirqs_off
569
	 nop
570
#endif
571
	mov		%l4, %o1
572
	mov		%l5, %o2
573
	call		cheetah_deferred_handler
574
	 add		%sp, PTREGS_OFF, %o0
575
	ba,a,pt		%xcc, rtrap_irq
576
	.size		c_deferred,.-c_deferred
577

578
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