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torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/arch/sparc/kernel/hvtramp.S
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/* SPDX-License-Identifier: GPL-2.0 */

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/* hvtramp.S: Hypervisor start-cpu trampoline code.

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 *

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 * Copyright (C) 2007, 2008 David S. Miller <[email protected]>

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 */

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#include <asm/thread_info.h>

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#include <asm/hypervisor.h>

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#include <asm/scratchpad.h>

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#include <asm/spitfire.h>

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#include <asm/hvtramp.h>

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#include <asm/pstate.h>

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#include <asm/ptrace.h>

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#include <asm/head.h>

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#include <asm/asi.h>

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#include <asm/pil.h>

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	.align		8

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	.globl		hv_cpu_startup, hv_cpu_startup_end

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	/* This code executes directly out of the hypervisor

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	 * with physical addressing (va==pa).  %o0 contains

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	 * our client argument which for Linux points to

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	 * a descriptor data structure which defines the

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	 * MMU entries we need to load up.

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	 *

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	 * After we set things up we enable the MMU and call

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	 * into the kernel.

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	 *

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	 * First setup basic privileged cpu state.

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	 */

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hv_cpu_startup:

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	SET_GL(0)

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	wrpr		%g0, PIL_NORMAL_MAX, %pil

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	wrpr		%g0, 0, %canrestore

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	wrpr		%g0, 0, %otherwin

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	wrpr		%g0, 6, %cansave

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	wrpr		%g0, 6, %cleanwin

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	wrpr		%g0, 0, %cwp

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	wrpr		%g0, 0, %wstate

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	wrpr		%g0, 0, %tl

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	sethi		%hi(sparc64_ttable_tl0), %g1

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	wrpr		%g1, %tba

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	mov		%o0, %l0

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	lduw		[%l0 + HVTRAMP_DESCR_CPU], %g1

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	mov		SCRATCHPAD_CPUID, %g2

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	stxa		%g1, [%g2] ASI_SCRATCHPAD

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	ldx		[%l0 + HVTRAMP_DESCR_FAULT_INFO_VA], %g2

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	stxa		%g2, [%g0] ASI_SCRATCHPAD

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	mov		0, %l1

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	lduw		[%l0 + HVTRAMP_DESCR_NUM_MAPPINGS], %l2

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	add		%l0, HVTRAMP_DESCR_MAPS, %l3

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1:	ldx		[%l3 + HVTRAMP_MAPPING_VADDR], %o0

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	clr		%o1

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	ldx		[%l3 + HVTRAMP_MAPPING_TTE], %o2

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	mov		HV_MMU_IMMU | HV_MMU_DMMU, %o3

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	mov		HV_FAST_MMU_MAP_PERM_ADDR, %o5

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	ta		HV_FAST_TRAP

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	brnz,pn		%o0, 80f

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	 nop

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	add		%l1, 1, %l1

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	cmp		%l1, %l2

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	blt,a,pt	%xcc, 1b

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	 add		%l3, HVTRAMP_MAPPING_SIZE, %l3

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	ldx		[%l0 + HVTRAMP_DESCR_FAULT_INFO_PA], %o0

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	mov		HV_FAST_MMU_FAULT_AREA_CONF, %o5

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	ta		HV_FAST_TRAP

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	brnz,pn		%o0, 80f

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	 nop

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	wrpr		%g0, (PSTATE_PRIV | PSTATE_PEF), %pstate

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	ldx		[%l0 + HVTRAMP_DESCR_THREAD_REG], %l6

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	mov		1, %o0

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	set		1f, %o1

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	mov		HV_FAST_MMU_ENABLE, %o5

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	ta		HV_FAST_TRAP

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	ba,pt		%xcc, 80f

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	 nop

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1:

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	wr		%g0, 0, %fprs

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	wr		%g0, ASI_P, %asi

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	mov		PRIMARY_CONTEXT, %g7

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	stxa		%g0, [%g7] ASI_MMU

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	membar		#Sync

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	mov		SECONDARY_CONTEXT, %g7

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	stxa		%g0, [%g7] ASI_MMU

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	membar		#Sync

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	mov		%l6, %g6

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	ldx		[%g6 + TI_TASK], %g4

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	mov		1, %g5

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	sllx		%g5, THREAD_SHIFT, %g5

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	sub		%g5, (STACKFRAME_SZ + STACK_BIAS), %g5

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	add		%g6, %g5, %sp

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	call		init_irqwork_curcpu

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	 nop

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	call		hard_smp_processor_id

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	 nop

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	call		sun4v_register_mondo_queues

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	 nop

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	call		init_cur_cpu_trap

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	 mov		%g6, %o0

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	wrpr		%g0, (PSTATE_PRIV | PSTATE_PEF | PSTATE_IE), %pstate

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	call		smp_callin

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	 nop

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	call		cpu_panic

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	 nop

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80:	ba,pt		%xcc, 80b

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	 nop

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	.align		8

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hv_cpu_startup_end:

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